ce701fd334
Merge pull request #744 from whitequark/write_verilog_$shift
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write_verilog: handle the $shift cell
2018-12-17 16:26:57 +01:00
d53a2bd1d3
anlogic: add support for Eagle Distributed RAM
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The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.
Enable to synthesis to DRAM.
As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-17 23:20:40 +08:00
634d7d1c14
Revert "Leave only real black box cells"
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This reverts commit 43030db5ff
2018-12-17 23:20:40 +08:00
dc6e63d8cd
Merge pull request #745 from YosysHQ/revert-714-abc_preserve_naming
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Revert "Proof-of-concept: preserve naming through ABC using dress"
2018-12-16 21:27:56 +01:00
2641a3089b
Revert "Proof-of-concept: preserve naming through ABC using dress"
2018-12-16 21:27:31 +01:00
ca866d384e
write_verilog: handle the $shift cell.
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The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:
module \\$shift (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (B_SIGNED) begin:BLOCK1
assign Y = $signed(B) < 0 ? A << -B : A >> B;
end else begin:BLOCK2
assign Y = A >> B;
end
endgenerate
endmodule
2018-12-16 18:46:32 +00:00
9f5c7017ff
Update CHANGELOG.
2018-12-16 18:26:00 +00:00
4effb38e6d
read_ilang: allow slicing sigspecs.
2018-12-16 17:53:26 +00:00
ddff75b60a
Merge pull request #736 from whitequark/select_assert_list
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select: print selection if a -assert-* flag causes an error
2018-12-16 16:45:49 +01:00
f6412d7109
select: print selection if a -assert-* flag causes an error.
2018-12-16 15:44:29 +00:00
5fa5dbbdda
Rename "fine:" label to "map:" in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 16:36:19 +01:00
4c5173045b
Merge pull request #704 from webhat/feature/fix-awk
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Using awk rather than gawk
2018-12-16 16:31:37 +01:00
fccaa25ec1
write_verilog: add a missing newline.
2018-12-16 15:22:34 +00:00
ac27a5a737
Merge pull request #738 from smunaut/issue_737
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verilog_parser: Properly handle recursion when processing attributes
2018-12-16 16:05:14 +01:00
0d9c850a07
Merge pull request #735 from daveshah1/trifixes
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deminout fixes
2018-12-16 16:02:21 +01:00
1e1452c7ff
Merge pull request #739 from whitequark/patch-1
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Add .editorconfig file
2018-12-16 16:01:13 +01:00
8f359cf1ff
Add .editorconfig file.
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See https://editorconfig.org/ for details.
2018-12-16 14:57:43 +00:00
f53e19cc71
Fix equiv_opt indenting
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-16 15:57:28 +01:00
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
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memory_bram: Fix initdata bit order after shuffling
2018-12-16 15:53:44 +01:00
ceffa66dbd
Merge pull request #730 from smunaut/ffssr_dont_touch
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ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-16 15:50:42 +01:00
f481ad4d44
Merge pull request #729 from whitequark/write_verilog_initial
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write_verilog: correctly map RTLIL `sync init`
2018-12-16 15:50:16 +01:00
0c69f1d777
Merge pull request #725 from olofk/ram4k-init
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Only use non-blocking assignments of SB_RAM40_4K for yosys
2018-12-16 15:42:04 +01:00
a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming
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Proof-of-concept: preserve naming through ABC using dress
2018-12-16 15:41:30 +01:00
9522eee02f
Merge pull request #723 from whitequark/synth_ice40_map_gates
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synth_ice40: split `map_gates` off `fine`
2018-12-16 15:30:08 +01:00
19ca4e2ac3
Merge pull request #722 from whitequark/rename_src
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rename: add -src, for inferring names from source locations
2018-12-16 15:28:29 +01:00
556341a77f
Merge pull request #720 from whitequark/master
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lut2mux: handle 1-bit INIT constant in $lut cells
2018-12-16 15:27:23 +01:00
58fb2ac818
verilog_parser: Properly handle recursion when processing attributes
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Fixes #737
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-14 12:48:00 +01:00
4c59447168
deminout: Consider $tribuf cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 17:17:40 +00:00
d3fe9465f3
deminout: Don't demote constant-driven inouts to inputs
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 16:50:46 +00:00
4fef9689ab
memory_bram: Fix initdata bit order after shuffling
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In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.
This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).
This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
2018-12-11 21:02:49 +00:00
0b9bb852c6
Add yosys-smtbmc support for btor witness
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-10 03:43:07 +01:00
add6ab9b2a
ice40: Honor the "dont_touch" attribute in FFSSR pass
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This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-08 22:46:28 +01:00
47a5dfdaa4
Add "yosys-smtbmc --btorwit" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-08 06:59:27 +01:00
ed3c57fad3
Fix btor init value handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-08 06:21:31 +01:00
7fe770a441
write_verilog: correctly map RTLIL `sync init`.
2018-12-07 18:55:08 +00:00
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
c38ea9ae65
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
435776120a
Merge pull request #727 from whitequark/opt_lut
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opt_lut: leave intact LUTs with cascade feeding module outputs
2018-12-07 17:17:26 +00:00
7ec740b7ad
opt_lut: leave intact LUTs with cascade feeding module outputs.
2018-12-07 17:13:52 +00:00
9eb03d458d
opt_lut: show original truth table for both cells.
2018-12-07 17:04:41 +00:00
a8ab722824
opt_lut: add -limit option, for debugging misoptimizations.
2018-12-07 16:36:26 +00:00
889297c62a
Only use non-blocking assignments of SB_RAM40_4K for yosys
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In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.
Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.
This patch will change to use non-blocking assignments only for yosys
2018-12-06 21:45:59 +01:00
1dfb2fecab
abc: Preserve naming through ABC using 'dress' command
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 15:05:07 +00:00
6e559ee3c7
synth_ice40: split `map_gates` off `fine`.
2018-12-06 12:04:39 +00:00
7d1088afc4
Add missing .gitignore
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:37 +01:00
643f858acf
Bugfix in opt_expr handling of a<0 and a>=0
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:21 +01:00
910d94b212
Verific updates
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:21:50 +01:00
a9baee4b24
rename: add -src, for inferring names from source locations.
2018-12-05 20:35:13 +00:00
d1f2cb01dc
lut2mux: handle 1-bit INIT constant in $lut cells.
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This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
2018-12-05 19:27:48 +00:00
Clifford Wolf
Icenowy Zheng
whitequark
Sylvain Munaut
David Shah
Graham Edgecombe
David Shah
Olof Kindgren