652050b273
Clean up `passes/memory/memory_collect.cc`.
2020-04-09 05:43:05 +00:00
685dc37d27
Clean up `passes/memory/memory_unpack.cc`.
2020-04-09 05:38:36 +00:00
83222193af
Clean up `passes/techmap/hilomap.cc`.
2020-04-09 05:28:32 +00:00
4737f426ff
write_cxxrtl: add basic documentation.
2020-04-09 04:08:36 +00:00
753e34007d
write_cxxrtl: add support for $dlatch and $dlatchsr cells.
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Also, fix codegen for $dffe and $adff.
2020-04-09 04:08:36 +00:00
711df56ad0
write_cxxrtl: add support for $sr cell.
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Also, fix the semantics of SET/CLR inputs of the $dffsr cell, and
fix the scheduling of async FF cells to consider ARST/SET/CLR->Q
as a forward combinatorial arc.
2020-04-09 04:08:36 +00:00
9534b51277
write_cxxrtl: add support for $slice and $concat cells.
2020-04-09 04:08:36 +00:00
01e6850bd3
write_cxxrtl: improve writable memory handling.
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This commit reduces space and time overhead for writable memories
to O(write port count) in both cases; implements handling for write
port priorities; and simplifies runtime representation of memories.
2020-04-09 04:08:36 +00:00
fb0270b752
write_cxxrtl: add support for hierarchical designs.
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Hierarchical design simulations are generally much slower, but this
comes with a major increase in flexibility:
1. Since the `flatten` pass currently does not support flattening
of designs with processes, this is the only way to simulate such
designs with cxxrtl.
2. Support for hierarchy paves way for simulation black boxes,
which are necessary for e.g. replacing PHYs with C++ code that
integrates with the host system.
2020-04-09 04:08:36 +00:00
3376dcf37c
write_cxxrtl: avoid undefined behavior on out-of-bounds memory access.
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After this commit, if NDEBUG is not defined, out-of-bounds accesses
cause assertion failures for reads and writes. If NDEBUG is defined,
out-of-bounds reads return zeroes, and out-of-bounds writes are
ignored.
This commit also adds support for memories that start with a non-zero
index (`Memory::start_offset` in RTLIL).
2020-04-09 04:08:36 +00:00
5157691f0e
write_cxxrtl: statically schedule comb logic and localize wires.
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This results in further massive gains in performance, modest decrease
in compile time, and, for designs without feedback arcs, makes it
possible to run eval() once per clock edge in certain conditions.
2020-04-09 04:08:36 +00:00
d6d7273421
write_cxxrtl: elide wires for results of comb cells used once.
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This results in massive gains in performance, equally massive
reduction in compile time, and improved readability.
2020-04-09 04:08:36 +00:00
d20e971725
write_cxxrtl: new backend.
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This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
2020-04-09 04:08:36 +00:00
42e7e44207
Merge pull request #1857 from whitequark/splitnets-skip-processes
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splitnets: skip modules with processes
2020-04-09 04:03:30 +00:00
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow
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Improve handling of integer literals in RTLIL frontend
2020-04-09 04:02:57 +00:00
570f43ec91
Merge pull request #1886 from boqwxp/cleanup_connect
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Clean up `passes/cmds/connect.cc`.
2020-04-09 03:58:07 +00:00
64a5936bd7
Clean up `passes/cmds/connect.cc`.
2020-04-08 22:11:06 +00:00
ac388859e3
Remove dependency on ilang backend since we no longer use it
2020-04-08 23:59:22 +02:00
9edf8869c1
Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
2020-04-08 23:50:37 +02:00
820e3d1dad
Remove unnecessary pruning of double-quoting
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In the past I was calling the ILANG_BACKEND::dump_const() to dump
values to an output stream. When these values were strings, the
function used to add quotes around them. The firrtl compiler, in turn,
escaped these quotes and the result was double-quoted strings which
were hard to read.
However I'm now calling design_entity->get_src_attribute() directly
and there is no additional quote being put around it, so we can
safely remove the unnecessary call to str.erase() here.
2020-04-08 23:20:56 +02:00
5f649fc19d
Add constids.inc to final install
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If this is not present in the install, #include-ing most yosys
headers will fail in rtlil.h:380.
2020-04-08 21:36:33 +02:00
5d18fdadfe
Merge pull request #1881 from hzeller/only-define-stdc-format-macros-if-not-already
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aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 13:56:40 -07:00
c15040c218
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
40223eaee1
Merge pull request #1814 from YosysHQ/mmicko/pyosys_makefile
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Enable ENABLE_LIBYOSYS when ENABLE_PYOSYS is set (closes #1813 )
2020-04-07 17:06:47 +02:00
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
194354e128
Remove `$anyconst` cells before specialization to eliminate warnings and the need to run `opt_clean`.
2020-04-07 03:29:54 +00:00
b350398c04
Merge pull request #1874 from boqwxp/cleanup_show
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Clean up `passes/cmds/show.cc`.
2020-04-06 18:32:20 +00:00
8ca12e0c42
Merge pull request #1861 from boqwxp/cleanup_hierarchy_submod
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Clean up `passes/hierarchy/submod.cc`.
2020-04-06 18:32:10 +00:00
b494d4c656
read_ilang: improve style. NFC.
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Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-06 18:31:15 +00:00
f4346a0400
Use more descriptive variable name.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-06 14:48:27 +00:00
d6de14a0d6
Use more descriptive variable name.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-04-06 14:37:07 +00:00
ebf23cd62e
Merge pull request #1870 from boqwxp/cleanup_setattr
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Clean up `passes/cmds/setattr.cc`.
2020-04-06 11:04:49 +00:00
df95dc7d4a
Merge pull request #1872 from boqwxp/cleanup_copy
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Clean up private member usage in `passes/cmds/copy.cc`.
2020-04-06 11:03:46 +00:00
41f0c38478
Merge pull request #1871 from boqwxp/cleanup_splice
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Clean up `passes/cmds/splice.cc`.
2020-04-06 11:03:34 +00:00
db66371915
Merge pull request #1869 from boqwxp/cleanup_connwrappers
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Clean up `passes/cmds/connwrappers.cc`.
2020-04-06 11:01:44 +00:00
30934e425d
Merge pull request #1868 from boqwxp/cleanup_delete
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Clean up `passes/cmds/delete.cc`.
2020-04-06 10:58:38 +00:00
d3615ee445
Merge pull request #1867 from boqwxp/cleanup_stat
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Clean up `passes/cmds/stat.cc`.
2020-04-06 10:58:02 +00:00
75d39c6fdf
Merge pull request #1866 from boqwxp/cleanup_test_autotb
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Clean up `passes/tests/test_autotb.cc`.
2020-04-06 10:56:45 +00:00
79c6149069
Merge pull request #1865 from boqwxp/cleanup_dfflibmap
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Clean up `passes/techmap/dfflibmap.cc`.
2020-04-06 10:56:22 +00:00
8340660518
Merge pull request #1863 from boqwxp/cleanup_techmap_extract
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Clean up `passes/techmap/extract.cc`.
2020-04-06 10:55:50 +00:00
0d69d532e0
Merge pull request #1859 from boqwxp/design_duplicate
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Add `-push-copy` option to the `design` command.
2020-04-06 10:39:26 +00:00
d22888ce74
read_ilang: improve error message for overly long wires.
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Fixes #1838 .
2020-04-06 10:33:02 +00:00
ca70a1049f
read_ilang: detect overflow of integer literals.
2020-04-06 10:32:02 +00:00
df69febb1e
Merge pull request #1873 from boqwxp/cleanup_bugpoint
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Clean up private member usage in `passes/cmds/bugpoint.cc`.
2020-04-06 10:13:06 +00:00
57f48f94c2
Clean up `passes/cmds/show.cc`.
2020-04-06 08:51:25 +00:00
fdeeb48e62
Clean up private member usage in `passes/cmds/bugpoint.cc`.
2020-04-06 08:35:09 +00:00
2dd09ab611
Clean up private member usage in `passes/cmds/copy.cc`.
2020-04-06 08:26:10 +00:00
5e9c88501e
Clean up `passes/cmds/splice.cc`.
2020-04-06 07:42:46 +00:00
2e27ddd511
Clean up `passes/cmds/setattr.cc`.
2020-04-06 06:52:18 +00:00
Alberto Gonzalez
whitequark
Sahand Kashani
Xiretza
Eddie Hung
Henner Zeller
Claire Wolf
Jeff Wang