18 Commits

Author	SHA1	Message	Date
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	2bec47a404	Use only module->addCell() and module->remove() to create and delete cells	2014-07-25 17:56:19 +02:00
Clifford Wolf	ec923652e2	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	2014-07-23 09:52:55 +02:00
Clifford Wolf	a8d3a68971	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	2014-07-23 09:49:43 +02:00
Clifford Wolf	260c19ec5a	Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	2014-07-23 09:34:47 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	1d88f1cf9f	Removed deprecated module->new_wire()	2014-07-21 12:35:06 +02:00
Clifford Wolf	3cb61d03f8	Wider range of cell types supported in "share" pass	2014-07-21 12:18:29 +02:00
Clifford Wolf	b49beab1f3	Use ezSAT::non_incremental() in "share" pass	2014-07-21 02:08:38 +02:00
Clifford Wolf	04fcb07213	Added support for resource sharing in mux control logic	2014-07-20 20:44:14 +02:00
Clifford Wolf	e9506bb2da	Supercell creation for $div/$mod worked all along, fixed test benches	2014-07-20 18:54:06 +02:00
Clifford Wolf	ff28029fdb	Fixed creation of shift supercells in "share" pass	2014-07-20 17:06:36 +02:00
Clifford Wolf	5b3ee7a072	Added "share" supercell creation	2014-07-20 15:01:17 +02:00
Clifford Wolf	7b98e46ac3	Added removing of always inactive cells to "share" pass	2014-07-20 13:24:36 +02:00
Clifford Wolf	8819493db4	Progress in "share" pass	2014-07-20 11:04:52 +02:00
Clifford Wolf	15fd615da5	Progress in "share" pass	2014-07-20 03:03:04 +02:00
Clifford Wolf	2278995bd8	Started to implement real resource sharing	2014-07-19 20:54:32 +02:00