bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer
...
The following SV module at HEAD imported with verific,
```systemverilog
module my_module(
input logic [4:0] a,
input logic clk,
input logic enable,
output logic [4:0] z
);
reg [4:0] pipeline_register;
always @(posedge clk) begin
pipeline_register <= enable ? a : pipeline_register;
end
assign z = pipeline_register;
endmodule : my_module
```
results in the following output verilog
```systemverilog
/* Generated by 0.36 */
(* top = 1 *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
wire [4:0] _0_;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
input [4:0] a;
wire [4:0] a;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
input clk;
wire clk;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
input enable;
wire enable;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
output [4:0] z;
wire [4:0] z;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
\$aldff #(
.ALOAD_POLARITY(32'd1),
.CLK_POLARITY(32'd1),
.WIDTH(32'd5)
) _1_ (
.AD(5'hxx),
.ALOAD(1'h0),
.CLK(clk),
.D(_0_),
.Q(z)
);
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
\$mux #(
.WIDTH(32'd5)
) _2_ (
.A(z),
.B(a),
.S(enable),
.Y(_0_)
);
endmodule
```
Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.
My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-05 07:10:25 +00:00
109b88c379
For case select values use Sa instead of Sx and Sz
2023-02-08 09:22:48 +01:00
b0be19c126
Support importing verilog configurations using Verific
2022-11-25 13:02:11 +01:00
96f64f4788
verific: Fix conditions of SVAs with explicit clocks within procedures
...
For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
2022-05-03 14:13:08 +02:00
245ecb0529
Import verific netlist in consistent order
2022-03-25 13:44:16 +01:00
1602a03864
Add support for $aldff flip-flops to verific importer
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2021-10-08 16:21:25 +02:00
72787f52fc
Fixing old e-mail addresses and deadnames
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s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ;
2021-06-08 00:39:36 +02:00
dd5f206d9e
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-27 08:43:54 -07:00
f6ff311a1d
Do not rename VHDL entities to "entity(impl)" when they are top modules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-20 12:54:10 +01:00
9260e97aa2
Automatically prune init attributes in verific front-end, fixes #1237
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 15:31:49 +02:00
3ea54ec400
Fix verific_parameters construction, use attribute to mark top netlists
2019-05-03 20:53:25 +02:00
a27b42e975
WIP -chparam support for hierarchy when verific
2019-05-03 20:53:25 +02:00
3d671630e2
Improve src tagging (using names and attrs) of cells and wires in verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-18 16:01:22 +01:00
5d9d22f66d
Add "verific -L <int>" option
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-04 20:06:10 +02:00
5f2bc1ce76
Add automatic verific import in hierarchy command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-20 23:45:01 +02:00
4372cf690d
Add (* gclk *) attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 13:25:42 +02:00
4d645f0fce
Fix verific handling of anyconst/anyseq attributes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-24 17:07:06 +02:00
ab8db2c168
Add "verific -autocover"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-06 14:10:57 +02:00
315d5e32bf
Fix handling of unclocked immediate assertions in Verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-26 13:04:10 +02:00
a4bbfd2d15
Fix Verific handling of "assert property (..);" in always block
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-07 20:06:02 +01:00
92d5f4db6f
Add "verific -import -V"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-07 19:40:34 +01:00
480e8e676a
Add proper SVA seq.triggered support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 19:29:26 +01:00
261cf706f4
Add VerificClocking class and refactor Verific DFF handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 13:48:53 +01:00
9a2a8cd97b
Fixes and improvements in Verific SVA importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-01 11:40:43 +01:00
15902d495f
Continue refactoring of Verific SVA importer code
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-28 11:45:04 +01:00
5fa2aa2741
Move Verific SVA importer to extra C++ source file
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-18 13:52:49 +01:00
Ethan Mahintorabi
Miodrag Milanovic
Jannis Harder
Claire Xenia Wolf
Eddie Hung
Clifford Wolf