mirror of https://github.com/YosysHQ/yosys.git
update type and variable names
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
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2d8343d423
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@ -80,7 +80,7 @@ struct statdata_t
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#undef X
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}
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statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_properties, string techname)
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statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_area, string techname)
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{
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tech = techname;
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@ -137,9 +137,9 @@ struct statdata_t
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cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
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}
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if (!cell_properties.empty()) {
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if (cell_properties.count(cell_type)) {
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cell_area_t cell_data = cell_properties.at(cell_type);
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if (!cell_area.empty()) {
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if (cell_area.count(cell_type)) {
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cell_area_t cell_data = cell_area.at(cell_type);
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if (cell_data.is_sequential) {
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sequential_area += cell_data.area;
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}
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@ -338,7 +338,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
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return mod_data;
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}
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void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_properties, string liberty_file)
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void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
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{
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std::ifstream f;
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f.open(liberty_file.c_str());
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@ -356,7 +356,7 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_properties, string
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LibertyAst *ar = cell->find("area");
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bool is_flip_flop = cell->find("ff") != nullptr;
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if (ar != nullptr && !ar->value.empty())
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cell_properties["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop};
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cell_area["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop};
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}
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}
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@ -397,7 +397,7 @@ struct StatPass : public Pass {
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bool width_mode = false, json_mode = false;
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RTLIL::Module *top_mod = nullptr;
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std::map<RTLIL::IdString, statdata_t> mod_stat;
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dict<IdString, cell_area_t> cell_properties;
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dict<IdString, cell_area_t> cell_area;
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string techname;
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size_t argidx;
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@ -410,7 +410,7 @@ struct StatPass : public Pass {
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if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
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string liberty_file = args[++argidx];
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rewrite_filename(liberty_file);
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read_liberty_cellarea(cell_properties, liberty_file);
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read_liberty_cellarea(cell_area, liberty_file);
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continue;
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}
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if (args[argidx] == "-tech" && argidx+1 < args.size()) {
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@ -453,7 +453,7 @@ struct StatPass : public Pass {
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if (mod->get_bool_attribute(ID::top))
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top_mod = mod;
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statdata_t data(design, mod, width_mode, cell_properties, techname);
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statdata_t data(design, mod, width_mode, cell_area, techname);
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mod_stat[mod->name] = data;
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if (json_mode) {
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