From f0df0e3912bdc40075a2762530d21add11c7e6d0 Mon Sep 17 00:00:00 2001
From: Ethan Mahintorabi <ethanmoon@google.com>
Date: Fri, 16 Feb 2024 00:01:44 +0000
Subject: [PATCH] update type and variable names

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
---
 passes/cmds/stat.cc | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 82ad80779..c74aa7c14 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -80,7 +80,7 @@ struct statdata_t
 	#undef X
 	}
 
-	statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_properties, string techname)
+	statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_area, string techname)
 	{
 		tech = techname;
 
@@ -137,9 +137,9 @@ struct statdata_t
 					cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
 			}
 
-			if (!cell_properties.empty()) {
-				if (cell_properties.count(cell_type)) {
-					cell_area_t cell_data = cell_properties.at(cell_type);
+			if (!cell_area.empty()) {
+				if (cell_area.count(cell_type)) {
+					cell_area_t cell_data = cell_area.at(cell_type);
 					if (cell_data.is_sequential) {
 						sequential_area += cell_data.area;
 					}
@@ -338,7 +338,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
 	return mod_data;
 }
 
-void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_properties, string liberty_file)
+void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
 {
 	std::ifstream f;
 	f.open(liberty_file.c_str());
@@ -356,7 +356,7 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_properties, string
 		LibertyAst *ar = cell->find("area");
 		bool is_flip_flop = cell->find("ff") != nullptr;
 		if (ar != nullptr && !ar->value.empty())
-			cell_properties["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop};
+			cell_area["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop};
 	}
 }
 
@@ -397,7 +397,7 @@ struct StatPass : public Pass {
 		bool width_mode = false, json_mode = false;
 		RTLIL::Module *top_mod = nullptr;
 		std::map<RTLIL::IdString, statdata_t> mod_stat;
-		dict<IdString, cell_area_t> cell_properties;
+		dict<IdString, cell_area_t> cell_area;
 		string techname;
 
 		size_t argidx;
@@ -410,7 +410,7 @@ struct StatPass : public Pass {
 			if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
 				string liberty_file = args[++argidx];
 				rewrite_filename(liberty_file);
-				read_liberty_cellarea(cell_properties, liberty_file);
+				read_liberty_cellarea(cell_area, liberty_file);
 				continue;
 			}
 			if (args[argidx] == "-tech" && argidx+1 < args.size()) {
@@ -453,7 +453,7 @@ struct StatPass : public Pass {
 				if (mod->get_bool_attribute(ID::top))
 					top_mod = mod;
 
-			statdata_t data(design, mod, width_mode, cell_properties, techname);
+			statdata_t data(design, mod, width_mode, cell_area, techname);
 			mod_stat[mod->name] = data;
 
 			if (json_mode) {