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update type and variable names 

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
This commit is contained in:
Ethan Mahintorabi 2024-02-16 00:01:44 +00:00
parent 2d8343d423
commit f0df0e3912
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GPG Key ID: 824E41B920BEA252
1 changed files with 9 additions and 9 deletions
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18
passes/cmds/stat.cc
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@ -80,7 +80,7 @@ struct statdata_t
#undef X #undef X
} }
statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_properties, string techname) statdata_t(RTLIL::Design *design, RTLIL::Module *mod, bool width_mode, const dict<IdString, cell_area_t> &cell_area, string techname)
{ {
tech = techname; tech = techname;
@ -137,9 +137,9 @@ struct statdata_t
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q))); cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
} }
if (!cell_properties.empty()) { if (!cell_area.empty()) {
if (cell_properties.count(cell_type)) { if (cell_area.count(cell_type)) {
cell_area_t cell_data = cell_properties.at(cell_type); cell_area_t cell_data = cell_area.at(cell_type);
if (cell_data.is_sequential) { if (cell_data.is_sequential) {
sequential_area += cell_data.area; sequential_area += cell_data.area;
} }
@ -338,7 +338,7 @@ statdata_t hierarchy_worker(std::map<RTLIL::IdString, statdata_t> &mod_stat, RTL
return mod_data; return mod_data;
} }
void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_properties, string liberty_file) void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_area, string liberty_file)
{ {
std::ifstream f; std::ifstream f;
f.open(liberty_file.c_str()); f.open(liberty_file.c_str());
@ -356,7 +356,7 @@ void read_liberty_cellarea(dict<IdString, cell_area_t> &cell_properties, string
LibertyAst *ar = cell->find("area"); LibertyAst *ar = cell->find("area");
bool is_flip_flop = cell->find("ff") != nullptr; bool is_flip_flop = cell->find("ff") != nullptr;
if (ar != nullptr && !ar->value.empty()) if (ar != nullptr && !ar->value.empty())
cell_properties["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop}; cell_area["\\" + cell->args[0]] = {/*area=*/atof(ar->value.c_str()), is_flip_flop};
} }
} }
@ -397,7 +397,7 @@ struct StatPass : public Pass {
bool width_mode = false, json_mode = false; bool width_mode = false, json_mode = false;
RTLIL::Module *top_mod = nullptr; RTLIL::Module *top_mod = nullptr;
std::map<RTLIL::IdString, statdata_t> mod_stat; std::map<RTLIL::IdString, statdata_t> mod_stat;
dict<IdString, cell_area_t> cell_properties; dict<IdString, cell_area_t> cell_area;
string techname; string techname;
size_t argidx; size_t argidx;
@ -410,7 +410,7 @@ struct StatPass : public Pass {
if (args[argidx] == "-liberty" && argidx+1 < args.size()) { if (args[argidx] == "-liberty" && argidx+1 < args.size()) {
string liberty_file = args[++argidx]; string liberty_file = args[++argidx];
rewrite_filename(liberty_file); rewrite_filename(liberty_file);
read_liberty_cellarea(cell_properties, liberty_file); read_liberty_cellarea(cell_area, liberty_file);
continue; continue;
} }
if (args[argidx] == "-tech" && argidx+1 < args.size()) { if (args[argidx] == "-tech" && argidx+1 < args.size()) {
@ -453,7 +453,7 @@ struct StatPass : public Pass {
if (mod->get_bool_attribute(ID::top)) if (mod->get_bool_attribute(ID::top))
top_mod = mod; top_mod = mod;
statdata_t data(design, mod, width_mode, cell_properties, techname); statdata_t data(design, mod, width_mode, cell_area, techname);
mod_stat[mod->name] = data; mod_stat[mod->name] = data;
if (json_mode) { if (json_mode) {