Merge remote-tracking branch 'origin/master' into xaig_arrival

Makefile

@@ -709,6 +709,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/opt && bash run-test.sh
 	+cd tests/aiger && bash run-test.sh $(ABCOPT)
 	+cd tests/arch && bash run-test.sh
+	+cd tests/ice40 && bash run-test.sh $(SEEDOPT)
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""

README.md

@@ -347,6 +347,20 @@ Verilog Attributes and non-standard features
   it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
   from inserting another pad cell on it.
 
+- The module attribute ``abc_box_id`` specifies a positive integer linking a
+  blackbox or whitebox definition to a corresponding entry in a `abc9`
+  box-file.
+
+- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
+  carry-out (if output port) ports of a box. This information is necessary for
+  `abc9` to preserve the integrity of carry-chains. Specifying this attribute
+  onto a bus port will affect only its most significant bit.
+
+- The port attribute ``abc_arrival`` specifies an integer (for output ports
+  only) to be used as the arrival time of this sequential port. It can be used,
+  for example, to specify the clk-to-Q delay of a flip-flop for consideration
+  during techmapping.
+
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset
@@ -423,20 +437,6 @@ Verilog Attributes and non-standard features
   blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
   functionality. (By default specify .. endspecify blocks are ignored.)
 
-- The module attribute ``abc_box_id`` specifies a positive integer linking a
-  blackbox or whitebox definition to a corresponding entry in a `abc9`
-  box-file.
-
-- The port attribute ``abc_carry`` marks the carry-in (if an input port) and
-  carry-out (if output port) ports of a box. This information is necessary for
-  `abc9` to preserve the integrity of carry-chains. Specifying this attribute
-  onto a bus port will affect only its most significant bit.
-
-- The port attribute ``abc_arrival`` specifies an integer (for output ports
-  only) to be used as the arrival time of this sequential port. It can be used,
-  for example, to specify the clk-to-Q delay of a flip-flop for consideration
-  during techmapping.
-
 
 Non-standard or SystemVerilog features for formal verification
 ==============================================================

frontends/aiger/aigerparse.cc

@@ -985,7 +985,7 @@ void AigerReader::post_process()
 	// operate (and run checks on) this one module
 	RTLIL::Design *mapped_design = new RTLIL::Design;
 	mapped_design->add(module);
-	Pass::call(mapped_design, "clean");
+	Pass::call(mapped_design, "clean -purge");
 	mapped_design->modules_.erase(module->name);
 	delete mapped_design;
 

passes/techmap/abc9.cc

@@ -668,30 +668,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		int in_wires = 0, out_wires = 0;
 
 		// Stitch in mapped_mod's inputs/outputs into module
-		for (auto &it : mapped_mod->wires_) {
+		for (auto port : mapped_mod->ports) {
-			RTLIL::Wire *w = it.second;
+			RTLIL::Wire *w = mapped_mod->wire(port);
-			if (!w->port_input && !w->port_output)
+			RTLIL::Wire *wire = module->wire(port);
-				continue;
-			RTLIL::Wire *wire = module->wire(w->name);
 			log_assert(wire);
-			RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
+			RTLIL::Wire *remap_wire = module->wire(remap_name(port));
 			RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
 			log_assert(GetSize(signal) >= GetSize(remap_wire));
 
-			log_assert(w->port_input || w->port_output);
 			RTLIL::SigSig conn;
-			if (w->port_input) {
-				conn.first = remap_wire;
-				conn.second = signal;
-				in_wires++;
-				module->connect(conn);
-			}
 			if (w->port_output) {
 				conn.first = signal;
 				conn.second = remap_wire;
 				out_wires++;
 				module->connect(conn);
 			}
+			else if (w->port_input) {
+				conn.first = remap_wire;
+				conn.second = signal;
+				in_wires++;
+				module->connect(conn);
+			}
 		}
 
 		for (auto &it : bit_users)
@@ -1274,9 +1271,6 @@ struct Abc9Pass : public Pass {
 
 		assign_map.clear();
 
-		// The "clean" pass also contains a design->check() call
-		Pass::call(design, "clean");
-
 		log_pop();
 	}
 } Abc9Pass;

tests/ice40/.gitignore

@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
++*_synth.v
++*_testbench

tests/ice40/add_sub.v

@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A =  x + y;
+assign B =  x - y;
+
+endmodule

tests/ice40/add_sub.ys

@@ -0,0 +1,9 @@
+read_verilog add_sub.v
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 11 t:SB_LUT4
+select -assert-count 6 t:SB_CARRY
+select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
+

tests/ice40/adffs.v

@@ -0,0 +1,91 @@
+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+endmodule

tests/ice40/adffs.ys

@@ -0,0 +1,12 @@
+read_verilog adffs.v
+proc
+async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFF
+select -assert-count 1 t:SB_DFFN
+select -assert-count 2 t:SB_DFFSR
+select -assert-count 7 t:SB_LUT4
+select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D

tests/ice40/alu.v

@@ -0,0 +1,19 @@
+module top (
+	input clock,
+	input [31:0] dinA, dinB,
+	input [2:0] opcode,
+	output reg [31:0] dout
+);
+	always @(posedge clock) begin
+		case (opcode)
+		0: dout <= dinA + dinB;
+		1: dout <= dinA - dinB;
+		2: dout <= dinA >> dinB;
+		3: dout <= $signed(dinA) >>> dinB;
+		4: dout <= dinA << dinB;
+		5: dout <= dinA & dinB;
+		6: dout <= dinA | dinB;
+		7: dout <= dinA ^ dinB;
+		endcase
+	end
+endmodule

tests/ice40/alu.ys

@@ -0,0 +1,11 @@
+read_verilog alu.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 62 t:SB_CARRY
+select -assert-count 32 t:SB_DFF
+select -assert-count 655 t:SB_LUT4
+select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D

tests/ice40/counter.v

@@ -0,0 +1,17 @@
+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+		if (reset) begin
+			out <= 8'b0 ;
+		end else
+			out <= out + 1;
+
+
+endmodule

tests/ice40/counter.ys

@@ -0,0 +1,11 @@
+read_verilog counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 6 t:SB_CARRY
+select -assert-count 8 t:SB_DFFR
+select -assert-count 8 t:SB_LUT4
+select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D

tests/ice40/dffs.v

@@ -0,0 +1,37 @@
+module dff
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule
+
+module top (
+input clk,
+input en,
+input a,
+output b,b1,
+);
+
+dff u_dff (
+        .clk (clk ),
+        .d (a ),
+        .q (b )
+    );
+
+dffe u_ndffe (
+        .clk (clk ),
+        .en (en),
+        .d (a ),
+        .q (b1 )
+    );
+
+endmodule

tests/ice40/dffs.ys

@@ -0,0 +1,10 @@
+read_verilog dffs.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFF
+select -assert-count 1 t:SB_DFFE
+select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D

tests/ice40/div_mod.v

@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A =  x % y;
+assign B =  x / y;
+
+endmodule

tests/ice40/div_mod.ys

@@ -0,0 +1,9 @@
+read_verilog div_mod.v
+hierarchy -top top
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 62 t:SB_LUT4
+select -assert-count 41 t:SB_CARRY
+select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D

tests/ice40/dpram.v

@@ -0,0 +1,23 @@
+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
+*/
+module top (din, write_en, waddr, wclk, raddr, rclk, dout);
+parameter addr_width = 8;
+parameter data_width = 8;
+input [addr_width-1:0] waddr, raddr;
+input [data_width-1:0] din;
+input write_en, wclk, rclk;
+output [data_width-1:0] dout;
+reg [data_width-1:0] dout;
+reg [data_width-1:0] mem [(1<<addr_width)-1:0]
+/* synthesis syn_ramstyle = "no_rw_check" */ ;
+always @(posedge wclk) // Write memory.
+begin
+if (write_en)
+mem[waddr] <= din; // Using write address bus.
+end
+always @(posedge rclk) // Read memory.
+begin
+dout <= mem[raddr]; // Using read address bus.
+end
+endmodule

tests/ice40/dpram.ys

@@ -0,0 +1,15 @@
+read_verilog dpram.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:SB_RAM40_4K
+select -assert-none t:SB_RAM40_4K %% t:* %D

tests/ice40/fsm.v

@@ -0,0 +1,73 @@
+ module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input   clock,reset,req_0,req_1;
+ output  gnt_0,gnt_1;
+ wire    clock,reset,req_0,req_1;
+ reg     gnt_0,gnt_1;
+
+ parameter SIZE = 3           ;
+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+   state <=  #1  IDLE;
+   gnt_0 <= 0;
+   gnt_1 <= 0;
+ end else
+  case(state)
+    IDLE : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+                 gnt_0 <= 1;
+               end else if (req_1 == 1'b1) begin
+                 gnt_1 <= 1;
+                 state <=  #1  GNT0;
+               end else begin
+                 state <=  #1  IDLE;
+               end
+    GNT0 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+               end else begin
+                 gnt_0 <= 0;
+                 state <=  #1  IDLE;
+               end
+    GNT1 : if (req_1 == 1'b1) begin
+                 state <=  #1  GNT2;
+				 gnt_1 <= req_0;
+               end
+    GNT2 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT1;
+				 gnt_1 <= req_1;
+               end
+    default : state <=  #1  IDLE;
+ endcase
+ end
+
+ endmodule
+
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+            .reset(rst),
+            .req_0(a),
+            .req_1(b),
+            .gnt_0(g0),
+            .gnt_1(g1));
+
+endmodule

tests/ice40/fsm.ys

@@ -0,0 +1,13 @@
+read_verilog fsm.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 2 t:SB_DFFESR
+select -assert-count 2 t:SB_DFFSR
+select -assert-count 1 t:SB_DFFSS
+select -assert-count 13 t:SB_LUT4
+select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D

tests/ice40/latches.v

@@ -0,0 +1,58 @@
+module latchp
+    ( input d, clk, en, output reg q );
+	always @*
+		if ( en )
+			q <= d;
+endmodule
+
+module latchn
+    ( input d, clk, en, output reg q );
+	always @*
+		if ( !en )
+			q <= d;
+endmodule
+
+module latchsr
+    ( input d, clk, en, clr, pre, output reg q );
+	always @*
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else if ( en )
+			q <= d;
+endmodule
+
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2
+);
+
+
+latchp u_latchp (
+        .en (clk ),
+        .d (a ),
+        .q (b )
+    );
+
+
+latchn u_latchn (
+        .en (clk ),
+        .d (a ),
+        .q (b1 )
+    );
+
+
+latchsr u_latchsr (
+        .en (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b2 )
+    );
+
+endmodule

tests/ice40/latches.ys

@@ -0,0 +1,15 @@
+read_verilog latches.v
+design -save read
+
+proc
+async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
+flatten
+synth_ice40
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+design -load read
+synth_ice40
+cd top
+select -assert-count 4 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D

tests/ice40/logic.v

@@ -0,0 +1,18 @@
+module top
+(
+ input [0:7] in,
+ output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+ );
+
+   assign     B1 =  in[0] & in[1];
+   assign     B2 =  in[0] | in[1];
+   assign     B3 =  in[0] ~& in[1];
+   assign     B4 =  in[0] ~| in[1];
+   assign     B5 =  in[0] ^ in[1];
+   assign     B6 =  in[0] ~^ in[1];
+   assign     B7 =  ~in[0];
+   assign     B8 =  in[0];
+   assign     B9 =  in[0:1] && in [2:3];
+   assign     B10 =  in[0:1] || in [2:3];
+
+endmodule

tests/ice40/logic.ys

@@ -0,0 +1,7 @@
+read_verilog logic.v
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 9 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D

tests/ice40/macc.v

@@ -0,0 +1,25 @@
+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
+*/
+module top(clk,a,b,c,set);
+parameter A_WIDTH = 4;
+parameter B_WIDTH = 3;
+input set;
+input clk;
+input signed [(A_WIDTH - 1):0] a;
+input signed [(B_WIDTH - 1):0] b;
+output signed [(A_WIDTH + B_WIDTH - 1):0] c;
+reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
+assign c = reg_tmp_c;
+always @(posedge clk)
+begin
+if(set)
+begin
+reg_tmp_c <= 0;
+end
+else
+begin
+reg_tmp_c <= a * b + c;
+end
+end
+endmodule

tests/ice40/macc.ys

@@ -0,0 +1,10 @@
+read_verilog macc.v
+proc
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 38 t:SB_LUT4
+select -assert-count 3 t:SB_CARRY
+select -assert-count 7 t:SB_DFFSR
+select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D

tests/ice40/memory.v

@@ -0,0 +1,21 @@
+module top
+(
+	input [7:0] data_a,
+	input [6:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		q_a <= ram[addr_a];
+	end
+endmodule

tests/ice40/memory.ys

@@ -0,0 +1,15 @@
+read_verilog memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:SB_RAM40_4K
+select -assert-none t:SB_RAM40_4K %% t:* %D

tests/ice40/mul.v

@@ -0,0 +1,11 @@
+module top
+(
+ input [5:0] x,
+ input [5:0] y,
+
+ output [11:0] A,
+ );
+
+assign A =  x * y;
+
+endmodule

tests/ice40/mul.ys

@@ -0,0 +1,7 @@
+read_verilog mul.v
+hierarchy -top top
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_MAC16
+select -assert-none t:SB_MAC16 %% t:* %D

tests/ice40/mux.v

@@ -0,0 +1,100 @@
+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

tests/ice40/mux.ys

@@ -0,0 +1,8 @@
+read_verilog mux.v
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 19 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D

tests/ice40/rom.v

@@ -0,0 +1,18 @@
+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
+*/
+module top(data, addr);
+output [3:0] data;
+input [4:0] addr;
+always @(addr) begin
+case (addr)
+0 : data = 'h4;
+1 : data = 'h9;
+2 : data = 'h1;
+15 : data = 'h8;
+16 : data = 'h1;
+17 : data = 'h0;
+default : data = 'h0;
+endcase
+end
+endmodule

tests/ice40/rom.ys

@@ -0,0 +1,8 @@
+read_verilog rom.v
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 5 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D

tests/ice40/run-test.sh

@@ -6,7 +6,7 @@ for x in *.ys; do
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log $x"
+	echo "	@../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then

tests/ice40/shifter.v

@@ -0,0 +1,22 @@
+module top    (
+out,
+clk,
+in
+);
+    output [7:0] out;
+    input signed clk, in;
+    reg signed [7:0] out = 0;
+
+    always @(posedge clk)
+	begin
+`ifndef BUG
+		out    <= out >> 1;
+		out[7] <= in;
+`else
+
+		out    <= out << 1;
+		out[7] <= in;
+`endif
+	end
+
+endmodule

tests/ice40/shifter.ys

@@ -0,0 +1,9 @@
+read_verilog shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:SB_DFF
+select -assert-none t:SB_DFF %% t:* %D

tests/ice40/tribuf.v

@@ -0,0 +1,23 @@
+module tristate (en, i, o);
+    input en;
+    input i;
+    output o;
+
+	assign o = en ? i : 1'bz;
+
+endmodule
+
+
+module top (
+input en,
+input a,
+output b
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (b )
+    );
+
+endmodule

tests/ice40/tribuf.ys

@@ -0,0 +1,9 @@
+read_verilog tribuf.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D

tests/simple_abc9/run-test.sh

@@ -20,4 +20,10 @@ fi
 cp ../simple/*.v .
 cp ../simple/*.sv .
 DOLLAR='?'
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\
+    hierarchy; \
+    synth -run coarse; \
+    opt -full; \
+    techmap; abc9 -lut 4 -box ../abc.box; \
+    check -assert; \
+    select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"