From 153ec0541c17ee8fad093c002a2724bc33dfe4b9 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 20 Aug 2019 07:50:05 +0300 Subject: [PATCH 01/43] Add new tests for ice40 architecture --- Makefile | 1 + tests/ice40/.gitignore | 1 + tests/ice40/add_sub.ys | 7 +++ tests/ice40/add_sub_tb.v | 47 +++++++++++++++++ tests/ice40/add_sub_top.v | 13 +++++ tests/ice40/common.v | 47 +++++++++++++++++ tests/ice40/dffs.ys | 5 ++ tests/ice40/dffs_tb.v | 77 +++++++++++++++++++++++++++ tests/ice40/dffs_top.v | 108 ++++++++++++++++++++++++++++++++++++++ tests/ice40/div_mod.ys | 5 ++ tests/ice40/div_mod_tb.v | 48 +++++++++++++++++ tests/ice40/div_mod_top.v | 13 +++++ tests/ice40/latches.ys | 5 ++ tests/ice40/latches_tb.v | 59 +++++++++++++++++++++ tests/ice40/latches_top.v | 58 ++++++++++++++++++++ tests/ice40/memory.ys | 7 +++ tests/ice40/memory_tb.v | 81 ++++++++++++++++++++++++++++ tests/ice40/memory_top.v | 21 ++++++++ tests/ice40/mul_pow.ys | 6 +++ tests/ice40/mul_pow_tb.v | 47 +++++++++++++++++ tests/ice40/mul_pow_top.v | 13 +++++ tests/ice40/mux.ys | 5 ++ tests/ice40/mux_tb.v | 43 +++++++++++++++ tests/ice40/mux_top.v | 100 +++++++++++++++++++++++++++++++++++ tests/ice40/run-test.sh | 21 ++++++++ tests/ice40/tribuf.ys | 6 +++ tests/ice40/tribuf_tb.v | 34 ++++++++++++ tests/ice40/tribuf_top.v | 23 ++++++++ 28 files changed, 901 insertions(+) create mode 100644 tests/ice40/.gitignore create mode 100644 tests/ice40/add_sub.ys create mode 100644 tests/ice40/add_sub_tb.v create mode 100644 tests/ice40/add_sub_top.v create mode 100644 tests/ice40/common.v create mode 100644 tests/ice40/dffs.ys create mode 100644 tests/ice40/dffs_tb.v create mode 100644 tests/ice40/dffs_top.v create mode 100644 tests/ice40/div_mod.ys create mode 100644 tests/ice40/div_mod_tb.v create mode 100644 tests/ice40/div_mod_top.v create mode 100644 tests/ice40/latches.ys create mode 100644 tests/ice40/latches_tb.v create mode 100644 tests/ice40/latches_top.v create mode 100644 tests/ice40/memory.ys create mode 100644 tests/ice40/memory_tb.v create mode 100644 tests/ice40/memory_top.v create mode 100644 tests/ice40/mul_pow.ys create mode 100644 tests/ice40/mul_pow_tb.v create mode 100644 tests/ice40/mul_pow_top.v create mode 100644 tests/ice40/mux.ys create mode 100644 tests/ice40/mux_tb.v create mode 100644 tests/ice40/mux_top.v create mode 100755 tests/ice40/run-test.sh create mode 100644 tests/ice40/tribuf.ys create mode 100644 tests/ice40/tribuf_tb.v create mode 100644 tests/ice40/tribuf_top.v diff --git a/Makefile b/Makefile index 382f79546..9cfa6a0de 100644 --- a/Makefile +++ b/Makefile @@ -699,6 +699,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/opt && bash run-test.sh +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh + +cd tests/ice40 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/ice40/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys new file mode 100644 index 000000000..58ad52a58 --- /dev/null +++ b/tests/ice40/add_sub.ys @@ -0,0 +1,7 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 12 t:SB_LUT4 +select -assert-count 7 t:SB_CARRY +select -assert-count 2 t:$logic_and +select -assert-count 2 t:$logic_or +write_verilog ./temp/add_sub_synth.v diff --git a/tests/ice40/add_sub_tb.v b/tests/ice40/add_sub_tb.v new file mode 100644 index 000000000..45e4f3154 --- /dev/null +++ b/tests/ice40/add_sub_tb.v @@ -0,0 +1,47 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] + in[7:4]; + assign poutB = in[3:0] - in[7:4]; + + check_comb add_test(outA, poutA); + check_comb sub_test(outB, poutB); + assert_comb sub0_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/add_sub_top.v b/tests/ice40/add_sub_top.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ice40/add_sub_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ice40/common.v b/tests/ice40/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ice40/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys new file mode 100644 index 000000000..68410b4d8 --- /dev/null +++ b/tests/ice40/dffs.ys @@ -0,0 +1,5 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFE +write_verilog ./temp/dffs_synth.v diff --git a/tests/ice40/dffs_tb.v b/tests/ice40/dffs_tb.v new file mode 100644 index 000000000..ed8f2eb2a --- /dev/null +++ b/tests/ice40/dffs_tb.v @@ -0,0 +1,77 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2,doutB3,doutB4; + reg dff,ndff,adff,adffn,dffe = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ), + .b3 (doutB3 ), + .b4 (doutB4 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @( posedge clk, posedge dinA[1], posedge dinA[2] ) + if ( dinA[2] ) + dff <= 1'b0; + else if ( dinA[1] ) + dff <= 1'b1; + else + dff <= dinA[0]; + + always @( negedge clk, negedge dinA[1], negedge dinA[2] ) + if ( !dinA[2] ) + ndff <= 1'b0; + else if ( !dinA[1] ) + ndff <= 1'b1; + else + ndff <= dinA[0]; + + always @( posedge clk, posedge dinA[2] ) + if ( dinA[2] ) + adff <= 1'b0; + else + adff <= dinA[0]; + + always @( posedge clk, negedge dinA[2] ) + if ( !dinA[2] ) + adffn <= 1'b0; + else + adffn <= dinA[0]; + + always @( posedge clk ) + if ( dinA[2] ) + dffe <= dinA[0]; + + assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); + assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); + assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); + assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); + assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); + +endmodule diff --git a/tests/ice40/dffs_top.v b/tests/ice40/dffs_top.v new file mode 100644 index 000000000..af7022c79 --- /dev/null +++ b/tests/ice40/dffs_top.v @@ -0,0 +1,108 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3,b4 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +dffe u_dffe ( + .clk (clk ), + .en (clr), + .d (a ), + .q (b4 ) + ); + +endmodule diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys new file mode 100644 index 000000000..28f31136b --- /dev/null +++ b/tests/ice40/div_mod.ys @@ -0,0 +1,5 @@ +synth_ice40 +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +select -assert-count 89 t:SB_LUT4 +select -assert-count 66 t:SB_CARRY +write_verilog ./temp/div_mod_synth.v diff --git a/tests/ice40/div_mod_tb.v b/tests/ice40/div_mod_tb.v new file mode 100644 index 000000000..4296535c9 --- /dev/null +++ b/tests/ice40/div_mod_tb.v @@ -0,0 +1,48 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] % in[7:4]; + assign poutB = in[3:0] / in[7:4]; + + check_comb mod_test(in[7:4], outA, poutA); + check_comb div_test(in[7:4], outB, poutB); + //assert_comb div2_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] divisor, input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (divisor != 4'b0000) + if (test !== pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/div_mod_top.v b/tests/ice40/div_mod_top.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ice40/div_mod_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys new file mode 100644 index 000000000..250ea0f84 --- /dev/null +++ b/tests/ice40/latches.ys @@ -0,0 +1,5 @@ +synth_ice40 +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +proc +select -assert-count 5 t:SB_LUT4 +write_verilog ./temp/latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v new file mode 100644 index 000000000..47ae8670c --- /dev/null +++ b/tests/ice40/latches_tb.v @@ -0,0 +1,59 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ice40/latches_top.v b/tests/ice40/latches_top.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ice40/latches_top.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys new file mode 100644 index 000000000..0f030d77d --- /dev/null +++ b/tests/ice40/memory.ys @@ -0,0 +1,7 @@ +proc +memory +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 8 t:SB_DFF +select -assert-count 512 t:SB_DFFE +write_verilog ./temp/memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v new file mode 100644 index 000000000..5905f3ddd --- /dev/null +++ b/tests/ice40/memory_tb.v @@ -0,0 +1,81 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/memory_top.v b/tests/ice40/memory_top.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ice40/memory_top.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ice40/mul_pow.ys b/tests/ice40/mul_pow.ys new file mode 100644 index 000000000..486480506 --- /dev/null +++ b/tests/ice40/mul_pow.ys @@ -0,0 +1,6 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 15 t:SB_LUT4 +select -assert-count 4 t:SB_CARRY +select -assert-count 1 t:$pow +write_verilog ./temp/mul_pow_synth.v diff --git a/tests/ice40/mul_pow_tb.v b/tests/ice40/mul_pow_tb.v new file mode 100644 index 000000000..7e888474f --- /dev/null +++ b/tests/ice40/mul_pow_tb.v @@ -0,0 +1,47 @@ +module testbench; + reg [7:0] in; + + wire [3:0] outA,outB; + wire [3:0] poutA,poutB; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 in = 0; + repeat (10000) begin + #5 in = in + 1; + end + + $display("OKAY"); + end + + top uut ( + .x(in[3:0]), + .y(in[7:4]), + .A(outA), + .B(outB) + ); + + + assign poutA = in[3:0] * in[7:4]; + assign poutB = in[3:0] ** in[7:4]; + + check_comb mul_test(outA, poutA); + check_comb pow_test(outB, poutB); + assert_comb pow2_test(outB[2], poutB[2]); + +endmodule + +module check_comb(input [3:0] test, input [3:0] pat); + always @* + begin + #1; + if (test !== pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); + $stop; + end + end +endmodule + diff --git a/tests/ice40/mul_pow_top.v b/tests/ice40/mul_pow_top.v new file mode 100644 index 000000000..6c256d96b --- /dev/null +++ b/tests/ice40/mul_pow_top.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x * y; +assign B = x ** y; + +endmodule diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys new file mode 100644 index 000000000..5ae5a1f33 --- /dev/null +++ b/tests/ice40/mux.ys @@ -0,0 +1,5 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 20 t:SB_LUT4 +select -assert-count 1 t:SB_CARRY +write_verilog ./temp/mux_synth.v diff --git a/tests/ice40/mux_tb.v b/tests/ice40/mux_tb.v new file mode 100644 index 000000000..2b2da25e9 --- /dev/null +++ b/tests/ice40/mux_tb.v @@ -0,0 +1,43 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [15:0] D = 1; + reg [3:0] S = 0; + wire M2,M4,M8,M16; + + top uut ( + .S (S ), + .D (D ), + .M2 (M2 ), + .M4 (M4 ), + .M8 (M8 ), + .M16 (M16 ) + ); + + always @(posedge clk) begin + //#3; + D <= {D[14:0],D[15]}; + //D <= D <<< 1; + S <= S + 1; + end + + assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2)); + assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4)); + assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8)); + assert_tri m16_test(.en(clk), .A(1'b1), .B(M16)); + +endmodule diff --git a/tests/ice40/mux_top.v b/tests/ice40/mux_top.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ice40/mux_top.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh new file mode 100755 index 000000000..e839aa9f5 --- /dev/null +++ b/tests/ice40/run-test.sh @@ -0,0 +1,21 @@ +#!/bin/bash +set -e +if [ -f "../../../../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../../../../techlibs/common + TECHLIBS_PREFIX=../../../../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +for x in *_top.v; do + echo "Running $x.." + ../../yosys -q -s ${x%_top.v}.ys -l ./temp/${x%.v}.log $x + echo "Simulating $x.." + iverilog -o ./temp/${x%_top.v}_testbench ${x%_top.v}_tb.v ./temp/${x%_top.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v + if ! vvp -N ./temp/${x%_top.v}_testbench > ./temp/${x%_top.v}_testbench.log 2>&1; then + grep 'ERROR' ./temp/${x%_top.v}_testbench.log + exit 0 + elif grep 'ERROR' ./temp/${x%_top.v}_testbench.log || ! grep 'OKAY' ./temp/${x%_top.v}_testbench.log; then + exit 0 + fi +done diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys new file mode 100644 index 000000000..40ded734d --- /dev/null +++ b/tests/ice40/tribuf.ys @@ -0,0 +1,6 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 1 t:SB_LUT4 +select -assert-count 1 t:SB_CARRY +select -assert-count 1 t:$_TBUF_ +write_verilog ./temp/tribuf_synth.v diff --git a/tests/ice40/tribuf_tb.v b/tests/ice40/tribuf_tb.v new file mode 100644 index 000000000..16871b7b2 --- /dev/null +++ b/tests/ice40/tribuf_tb.v @@ -0,0 +1,34 @@ +module testbench; + reg en; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 en = 0; + repeat (10000) begin + #5 en = 1; + #5 en = 0; + end + + $display("OKAY"); + end + + + reg dinA = 0; + wire doutB; + + top uut ( + .en (en ), + .a (dinA ), + .b (doutB ) + ); + + always @(posedge en) begin + #3; + dinA <= !dinA; + end + + assert_tri b_test(.en(en), .A(dinA), .B(doutB)); + +endmodule diff --git a/tests/ice40/tribuf_top.v b/tests/ice40/tribuf_top.v new file mode 100644 index 000000000..b2b5e37d6 --- /dev/null +++ b/tests/ice40/tribuf_top.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule From 71dd412ac55860cbf51d91d26088515978f70116 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 20 Aug 2019 15:52:25 +0300 Subject: [PATCH 02/43] Fix tests; Remove simulation; - Add -map and -assert options for equiv_opt; !!! '-assert' option was commented for the next tests (unproven $equiv cells was found): - dffs; - div_mod; - latches; - mul_pow; - Add design -load; - Remove simulations; --- tests/ice40/{add_sub_top.v => add_sub.v} | 0 tests/ice40/add_sub.ys | 4 +- tests/ice40/add_sub_tb.v | 47 -------------- tests/ice40/common.v | 47 -------------- tests/ice40/{dffs_top.v => dffs.v} | 0 tests/ice40/dffs.ys | 11 +++- tests/ice40/dffs_tb.v | 77 ---------------------- tests/ice40/{div_mod_top.v => div_mod.v} | 0 tests/ice40/div_mod.ys | 9 +-- tests/ice40/div_mod_tb.v | 48 -------------- tests/ice40/{latches_top.v => latches.v} | 0 tests/ice40/latches.ys | 5 +- tests/ice40/latches_tb.v | 59 ----------------- tests/ice40/{memory_top.v => memory.v} | 0 tests/ice40/memory.ys | 5 +- tests/ice40/memory_tb.v | 81 ------------------------ tests/ice40/{mul_pow_top.v => mul_pow.v} | 0 tests/ice40/mul_pow.ys | 7 +- tests/ice40/mul_pow_tb.v | 47 -------------- tests/ice40/{mux_top.v => mux.v} | 0 tests/ice40/mux.ys | 5 +- tests/ice40/mux_tb.v | 43 ------------- tests/ice40/run-test.sh | 19 +----- tests/ice40/{tribuf_top.v => tribuf.v} | 0 tests/ice40/tribuf.ys | 4 +- tests/ice40/tribuf_tb.v | 34 ---------- 26 files changed, 33 insertions(+), 519 deletions(-) rename tests/ice40/{add_sub_top.v => add_sub.v} (100%) delete mode 100644 tests/ice40/add_sub_tb.v delete mode 100644 tests/ice40/common.v rename tests/ice40/{dffs_top.v => dffs.v} (100%) delete mode 100644 tests/ice40/dffs_tb.v rename tests/ice40/{div_mod_top.v => div_mod.v} (100%) delete mode 100644 tests/ice40/div_mod_tb.v rename tests/ice40/{latches_top.v => latches.v} (100%) delete mode 100644 tests/ice40/latches_tb.v rename tests/ice40/{memory_top.v => memory.v} (100%) delete mode 100644 tests/ice40/memory_tb.v rename tests/ice40/{mul_pow_top.v => mul_pow.v} (100%) delete mode 100644 tests/ice40/mul_pow_tb.v rename tests/ice40/{mux_top.v => mux.v} (100%) delete mode 100644 tests/ice40/mux_tb.v rename tests/ice40/{tribuf_top.v => tribuf.v} (100%) delete mode 100644 tests/ice40/tribuf_tb.v diff --git a/tests/ice40/add_sub_top.v b/tests/ice40/add_sub.v similarity index 100% rename from tests/ice40/add_sub_top.v rename to tests/ice40/add_sub.v diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index 58ad52a58..c2ee3a843 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,7 +1,7 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +design -load postopt select -assert-count 12 t:SB_LUT4 select -assert-count 7 t:SB_CARRY select -assert-count 2 t:$logic_and select -assert-count 2 t:$logic_or -write_verilog ./temp/add_sub_synth.v diff --git a/tests/ice40/add_sub_tb.v b/tests/ice40/add_sub_tb.v deleted file mode 100644 index 45e4f3154..000000000 --- a/tests/ice40/add_sub_tb.v +++ /dev/null @@ -1,47 +0,0 @@ -module testbench; - reg [7:0] in; - - wire [3:0] outA,outB; - wire [3:0] poutA,poutB; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 in = 0; - repeat (10000) begin - #5 in = in + 1; - end - - $display("OKAY"); - end - - top uut ( - .x(in[3:0]), - .y(in[7:4]), - .A(outA), - .B(outB) - ); - - - assign poutA = in[3:0] + in[7:4]; - assign poutB = in[3:0] - in[7:4]; - - check_comb add_test(outA, poutA); - check_comb sub_test(outB, poutB); - assert_comb sub0_test(outB[2], poutB[2]); - -endmodule - -module check_comb(input [3:0] test, input [3:0] pat); - always @* - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); - $stop; - end - end -endmodule - diff --git a/tests/ice40/common.v b/tests/ice40/common.v deleted file mode 100644 index 5446f0817..000000000 --- a/tests/ice40/common.v +++ /dev/null @@ -1,47 +0,0 @@ -module assert_dff(input clk, input test, input pat); - always @(posedge clk) - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time); - $stop; - end - end -endmodule - -module assert_tri(input en, input A, input B); - always @(posedge en) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule - -module assert_Z(input clk, input A); - always @(posedge clk) - begin - #1; - if (A === 1'bZ) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); - $stop; - end - end -endmodule - -module assert_comb(input A, input B); - always @(*) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ice40/dffs_top.v b/tests/ice40/dffs.v similarity index 100% rename from tests/ice40/dffs_top.v rename to tests/ice40/dffs.v diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index 68410b4d8..09b7bc25a 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,5 +1,12 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +proc +flatten +dff2dffe synth_ice40 +#equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 +design -load postopt select -assert-count 2 t:SB_DFFR select -assert-count 1 t:SB_DFFE -write_verilog ./temp/dffs_synth.v +select -assert-count 4 t:SB_LUT4 +select -assert-count 1 t:$_DFFSR_PPP_ +select -assert-count 1 t:$_DFFSR_NPP_ diff --git a/tests/ice40/dffs_tb.v b/tests/ice40/dffs_tb.v deleted file mode 100644 index ed8f2eb2a..000000000 --- a/tests/ice40/dffs_tb.v +++ /dev/null @@ -1,77 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2,doutB3,doutB4; - reg dff,ndff,adff,adffn,dffe = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ), - .b3 (doutB3 ), - .b4 (doutB4 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @( posedge clk, posedge dinA[1], posedge dinA[2] ) - if ( dinA[2] ) - dff <= 1'b0; - else if ( dinA[1] ) - dff <= 1'b1; - else - dff <= dinA[0]; - - always @( negedge clk, negedge dinA[1], negedge dinA[2] ) - if ( !dinA[2] ) - ndff <= 1'b0; - else if ( !dinA[1] ) - ndff <= 1'b1; - else - ndff <= dinA[0]; - - always @( posedge clk, posedge dinA[2] ) - if ( dinA[2] ) - adff <= 1'b0; - else - adff <= dinA[0]; - - always @( posedge clk, negedge dinA[2] ) - if ( !dinA[2] ) - adffn <= 1'b0; - else - adffn <= dinA[0]; - - always @( posedge clk ) - if ( dinA[2] ) - dffe <= dinA[0]; - - assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); - assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); - assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); - assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); - assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); - -endmodule diff --git a/tests/ice40/div_mod_top.v b/tests/ice40/div_mod.v similarity index 100% rename from tests/ice40/div_mod_top.v rename to tests/ice40/div_mod.v diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 28f31136b..f66cb99dd 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,5 +1,6 @@ synth_ice40 -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 -select -assert-count 89 t:SB_LUT4 -select -assert-count 66 t:SB_CARRY -write_verilog ./temp/div_mod_synth.v +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v synth_ice40 +design -load postopt +select -assert-count 85 t:SB_LUT4 +select -assert-count 54 t:SB_CARRY diff --git a/tests/ice40/div_mod_tb.v b/tests/ice40/div_mod_tb.v deleted file mode 100644 index 4296535c9..000000000 --- a/tests/ice40/div_mod_tb.v +++ /dev/null @@ -1,48 +0,0 @@ -module testbench; - reg [7:0] in; - - wire [3:0] outA,outB; - wire [3:0] poutA,poutB; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 in = 0; - repeat (10000) begin - #5 in = in + 1; - end - - $display("OKAY"); - end - - top uut ( - .x(in[3:0]), - .y(in[7:4]), - .A(outA), - .B(outB) - ); - - - assign poutA = in[3:0] % in[7:4]; - assign poutB = in[3:0] / in[7:4]; - - check_comb mod_test(in[7:4], outA, poutA); - check_comb div_test(in[7:4], outB, poutB); - //assert_comb div2_test(outB[2], poutB[2]); - -endmodule - -module check_comb(input [3:0] divisor, input [3:0] test, input [3:0] pat); - always @* - begin - #1; - if (divisor != 4'b0000) - if (test !== pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); - $stop; - end - end -endmodule - diff --git a/tests/ice40/latches_top.v b/tests/ice40/latches.v similarity index 100% rename from tests/ice40/latches_top.v rename to tests/ice40/latches.v diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index 250ea0f84..77037b1d5 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,5 +1,6 @@ synth_ice40 -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v synth_ice40 +design -load postopt proc select -assert-count 5 t:SB_LUT4 -write_verilog ./temp/latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v deleted file mode 100644 index 47ae8670c..000000000 --- a/tests/ice40/latches_tb.v +++ /dev/null @@ -1,59 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2; - reg lat,latn,latsr = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @* - if ( clk ) - lat <= dinA[0]; - - - always @* - if ( !clk ) - latn <= dinA[0]; - - - always @* - if ( dinA[2] ) - latsr <= 1'b0; - else if ( dinA[1] ) - latsr <= 1'b1; - else if ( clk ) - latsr <= dinA[0]; - - assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); - assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); - assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); - -endmodule diff --git a/tests/ice40/memory_top.v b/tests/ice40/memory.v similarity index 100% rename from tests/ice40/memory_top.v rename to tests/ice40/memory.v diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index 0f030d77d..47d5526c1 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,7 +1,8 @@ proc memory -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +design -load postopt + select -assert-count 8 t:SB_DFF select -assert-count 512 t:SB_DFFE -write_verilog ./temp/memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v deleted file mode 100644 index 5905f3ddd..000000000 --- a/tests/ice40/memory_tb.v +++ /dev/null @@ -1,81 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [7:0] data_a = 0; - reg [5:0] addr_a = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - top uut ( - .data_a(data_a), - .addr_a(addr_a), - .we_a(we_a), - .clk(clk), - .q_a(q_a) - ); - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - // Declare the RAM variable for check - reg [7:0] ram[63:0]; - - // Port A for check - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - pq_a <= data_a; - end - pq_a <= ram[addr_a]; - end - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ice40/mul_pow_top.v b/tests/ice40/mul_pow.v similarity index 100% rename from tests/ice40/mul_pow_top.v rename to tests/ice40/mul_pow.v diff --git a/tests/ice40/mul_pow.ys b/tests/ice40/mul_pow.ys index 486480506..2a6baa738 100644 --- a/tests/ice40/mul_pow.ys +++ b/tests/ice40/mul_pow.ys @@ -1,6 +1,7 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 synth_ice40 -select -assert-count 15 t:SB_LUT4 +#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +equiv_opt -map +/ice40/cells_sim.v synth_ice40 +design -load postopt +select -assert-count 16 t:SB_LUT4 select -assert-count 4 t:SB_CARRY select -assert-count 1 t:$pow -write_verilog ./temp/mul_pow_synth.v diff --git a/tests/ice40/mul_pow_tb.v b/tests/ice40/mul_pow_tb.v deleted file mode 100644 index 7e888474f..000000000 --- a/tests/ice40/mul_pow_tb.v +++ /dev/null @@ -1,47 +0,0 @@ -module testbench; - reg [7:0] in; - - wire [3:0] outA,outB; - wire [3:0] poutA,poutB; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 in = 0; - repeat (10000) begin - #5 in = in + 1; - end - - $display("OKAY"); - end - - top uut ( - .x(in[3:0]), - .y(in[7:4]), - .A(outA), - .B(outB) - ); - - - assign poutA = in[3:0] * in[7:4]; - assign poutB = in[3:0] ** in[7:4]; - - check_comb mul_test(outA, poutA); - check_comb pow_test(outB, poutB); - assert_comb pow2_test(outB[2], poutB[2]); - -endmodule - -module check_comb(input [3:0] test, input [3:0] pat); - always @* - begin - #1; - if (test !== pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat); - $stop; - end - end -endmodule - diff --git a/tests/ice40/mux_top.v b/tests/ice40/mux.v similarity index 100% rename from tests/ice40/mux_top.v rename to tests/ice40/mux.v diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 5ae5a1f33..3da9ef433 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,5 +1,6 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 + synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 +design -load postopt select -assert-count 20 t:SB_LUT4 select -assert-count 1 t:SB_CARRY -write_verilog ./temp/mux_synth.v diff --git a/tests/ice40/mux_tb.v b/tests/ice40/mux_tb.v deleted file mode 100644 index 2b2da25e9..000000000 --- a/tests/ice40/mux_tb.v +++ /dev/null @@ -1,43 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [15:0] D = 1; - reg [3:0] S = 0; - wire M2,M4,M8,M16; - - top uut ( - .S (S ), - .D (D ), - .M2 (M2 ), - .M4 (M4 ), - .M8 (M8 ), - .M16 (M16 ) - ); - - always @(posedge clk) begin - //#3; - D <= {D[14:0],D[15]}; - //D <= D <<< 1; - S <= S + 1; - end - - assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2)); - assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4)); - assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8)); - assert_tri m16_test(.en(clk), .A(1'b1), .B(M16)); - -endmodule diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index e839aa9f5..75e5f0609 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -1,21 +1,6 @@ #!/bin/bash set -e -if [ -f "../../../../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../../../../techlibs/common - TECHLIBS_PREFIX=../../../../../techlibs -else - COMMON_PREFIX=/usr/local/share/yosys - TECHLIBS_PREFIX=/usr/local/share/yosys -fi -for x in *_top.v; do +for x in *.v; do echo "Running $x.." - ../../yosys -q -s ${x%_top.v}.ys -l ./temp/${x%.v}.log $x - echo "Simulating $x.." - iverilog -o ./temp/${x%_top.v}_testbench ${x%_top.v}_tb.v ./temp/${x%_top.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v - if ! vvp -N ./temp/${x%_top.v}_testbench > ./temp/${x%_top.v}_testbench.log 2>&1; then - grep 'ERROR' ./temp/${x%_top.v}_testbench.log - exit 0 - elif grep 'ERROR' ./temp/${x%_top.v}_testbench.log || ! grep 'OKAY' ./temp/${x%_top.v}_testbench.log; then - exit 0 - fi + ../../yosys -q -s ${x%.v}.ys -l ./temp/${x%.v}.log $x done diff --git a/tests/ice40/tribuf_top.v b/tests/ice40/tribuf.v similarity index 100% rename from tests/ice40/tribuf_top.v rename to tests/ice40/tribuf.v diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index 40ded734d..b319e6622 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -1,6 +1,6 @@ -equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 +design -load postopt select -assert-count 1 t:SB_LUT4 select -assert-count 1 t:SB_CARRY select -assert-count 1 t:$_TBUF_ -write_verilog ./temp/tribuf_synth.v diff --git a/tests/ice40/tribuf_tb.v b/tests/ice40/tribuf_tb.v deleted file mode 100644 index 16871b7b2..000000000 --- a/tests/ice40/tribuf_tb.v +++ /dev/null @@ -1,34 +0,0 @@ -module testbench; - reg en; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 en = 0; - repeat (10000) begin - #5 en = 1; - #5 en = 0; - end - - $display("OKAY"); - end - - - reg dinA = 0; - wire doutB; - - top uut ( - .en (en ), - .a (dinA ), - .b (doutB ) - ); - - always @(posedge en) begin - #3; - dinA <= !dinA; - end - - assert_tri b_test(.en(en), .A(dinA), .B(doutB)); - -endmodule From b835ec37cbb56bc3b55fe53eb85375ad5ac98f27 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 21 Aug 2019 07:53:34 +0300 Subject: [PATCH 03/43] Add temp directory --- tests/ice40/temp/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 tests/ice40/temp/.gitignore diff --git a/tests/ice40/temp/.gitignore b/tests/ice40/temp/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/ice40/temp/.gitignore @@ -0,0 +1 @@ +*.log From d945b8a357c567f5f3565983da09f24c0f295461 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 21 Aug 2019 21:52:07 +0300 Subject: [PATCH 04/43] Fix all comments from PR --- tests/ice40/add_sub.ys | 17 +++-- tests/ice40/adffs.v | 108 +++++++++++++++++++++++++++++++ tests/ice40/adffs.ys | 9 +++ tests/ice40/adffs_tb.v | 75 +++++++++++++++++++++ tests/ice40/common.v | 47 ++++++++++++++ tests/ice40/dffs.v | 107 +----------------------------- tests/ice40/dffs.ys | 17 +++-- tests/ice40/div_mod.ys | 15 +++-- tests/ice40/latches.ys | 7 +- tests/ice40/latches_tb.v | 59 +++++++++++++++++ tests/ice40/memory.ys | 10 +-- tests/ice40/memory_tb.v | 81 +++++++++++++++++++++++ tests/ice40/{mul_pow.v => mul.v} | 1 - tests/ice40/mul.ys | 9 +++ tests/ice40/mul_pow.ys | 7 -- tests/ice40/mux.ys | 2 +- tests/ice40/run-test.sh | 35 ++++++++-- tests/ice40/temp/.gitignore | 1 - tests/ice40/tribuf.v | 6 +- tests/ice40/tribuf.ys | 12 ++-- 20 files changed, 465 insertions(+), 160 deletions(-) create mode 100644 tests/ice40/adffs.v create mode 100644 tests/ice40/adffs.ys create mode 100644 tests/ice40/adffs_tb.v create mode 100644 tests/ice40/common.v create mode 100644 tests/ice40/latches_tb.v create mode 100644 tests/ice40/memory_tb.v rename tests/ice40/{mul_pow.v => mul.v} (85%) create mode 100644 tests/ice40/mul.ys delete mode 100644 tests/ice40/mul_pow.ys delete mode 100644 tests/ice40/temp/.gitignore diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index c2ee3a843..84f31ec53 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,7 +1,10 @@ -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -select -assert-count 12 t:SB_LUT4 -select -assert-count 7 t:SB_CARRY -select -assert-count 2 t:$logic_and -select -assert-count 2 t:$logic_or +read_verilog add_sub.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D + diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v new file mode 100644 index 000000000..af7022c79 --- /dev/null +++ b/tests/ice40/adffs.v @@ -0,0 +1,108 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3,b4 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +dffe u_dffe ( + .clk (clk ), + .en (clr), + .d (a ), + .q (b4 ) + ); + +endmodule diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys new file mode 100644 index 000000000..aee8cd6b4 --- /dev/null +++ b/tests/ice40/adffs.ys @@ -0,0 +1,9 @@ +read_verilog adffs.v +proc +dff2dffe +synth_ice40 +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFE +select -assert-count 4 t:SB_LUT4 +#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D +write_verilog adffs_synth.v diff --git a/tests/ice40/adffs_tb.v b/tests/ice40/adffs_tb.v new file mode 100644 index 000000000..e049edabc --- /dev/null +++ b/tests/ice40/adffs_tb.v @@ -0,0 +1,75 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2,doutB3,doutB4; + reg dff,ndff,adff,adffn,dffe = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @( posedge clk, posedge dinA[1], posedge dinA[2] ) + if ( dinA[2] ) + dff <= 1'b0; + else if ( dinA[1] ) + dff <= 1'b1; + else + dff <= dinA[0]; + + always @( negedge clk, negedge dinA[1], negedge dinA[2] ) + if ( !dinA[2] ) + ndff <= 1'b0; + else if ( !dinA[1] ) + ndff <= 1'b1; + else + ndff <= dinA[0]; + + always @( posedge clk, posedge dinA[2] ) + if ( dinA[2] ) + adff <= 1'b0; + else + adff <= dinA[0]; + + always @( posedge clk, negedge dinA[2] ) + if ( !dinA[2] ) + adffn <= 1'b0; + else + adffn <= dinA[0]; + + always @( posedge clk ) + if ( dinA[2] ) + dffe <= dinA[0]; + + assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); + assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); + assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); + //assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); + //assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); + +endmodule diff --git a/tests/ice40/common.v b/tests/ice40/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ice40/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v index af7022c79..d57c8c97c 100644 --- a/tests/ice40/dffs.v +++ b/tests/ice40/dffs.v @@ -1,108 +1,5 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end +module top + ( input d, clk, output reg q ); always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module dffsr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else q <= d; endmodule - -module ndffnsnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3,b4 -); - -dffsr u_dffsr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnsnr u_ndffnsnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -dffe u_dffe ( - .clk (clk ), - .en (clr), - .d (a ), - .q (b4 ) - ); - -endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index 09b7bc25a..0fa0bc3eb 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,12 +1,11 @@ +read_verilog dffs.v proc flatten dff2dffe -synth_ice40 -#equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 -equiv_opt -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 -design -load postopt -select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFE -select -assert-count 4 t:SB_LUT4 -select -assert-count 1 t:$_DFFSR_PPP_ -select -assert-count 1 t:$_DFFSR_NPP_ +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index f66cb99dd..93285cede 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,6 +1,9 @@ -synth_ice40 -#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -equiv_opt -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -select -assert-count 85 t:SB_LUT4 -select -assert-count 54 t:SB_CARRY +read_verilog div_mod.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 88 t:SB_LUT4 +select -assert-count 65 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index 77037b1d5..0abd7f195 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,6 +1,5 @@ +read_verilog latches.v synth_ice40 -#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -equiv_opt -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -proc select -assert-count 5 t:SB_LUT4 +#select -assert-none t:SB_LUT4 %% t:* %D +write_verilog latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v new file mode 100644 index 000000000..47ae8670c --- /dev/null +++ b/tests/ice40/latches_tb.v @@ -0,0 +1,59 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index 47d5526c1..a0391e93d 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,8 +1,4 @@ -proc -memory +read_verilog memory.v synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -design -load postopt - -select -assert-count 8 t:SB_DFF -select -assert-count 512 t:SB_DFFE +select -assert-count 1 t:SB_RAM40_4K +write_verilog memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v new file mode 100644 index 000000000..5905f3ddd --- /dev/null +++ b/tests/ice40/memory_tb.v @@ -0,0 +1,81 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + + $display("OKAY"); + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/mul_pow.v b/tests/ice40/mul.v similarity index 85% rename from tests/ice40/mul_pow.v rename to tests/ice40/mul.v index 6c256d96b..c099db0d9 100644 --- a/tests/ice40/mul_pow.v +++ b/tests/ice40/mul.v @@ -8,6 +8,5 @@ module top ); assign A = x * y; -assign B = x ** y; endmodule diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys new file mode 100644 index 000000000..35048d14a --- /dev/null +++ b/tests/ice40/mul.ys @@ -0,0 +1,9 @@ +read_verilog mul.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 15 t:SB_LUT4 +select -assert-count 3 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/ice40/mul_pow.ys b/tests/ice40/mul_pow.ys deleted file mode 100644 index 2a6baa738..000000000 --- a/tests/ice40/mul_pow.ys +++ /dev/null @@ -1,7 +0,0 @@ -synth_ice40 -#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -equiv_opt -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -select -assert-count 16 t:SB_LUT4 -select -assert-count 4 t:SB_CARRY -select -assert-count 1 t:$pow diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 3da9ef433..9e3d87b7f 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,4 +1,4 @@ - +read_verilog mux.v synth_ice40 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 design -load postopt diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 75e5f0609..5bd9fb173 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -1,6 +1,33 @@ -#!/bin/bash set -e -for x in *.v; do - echo "Running $x.." - ../../yosys -q -s ${x%.v}.ys -l ./temp/${x%.v}.log $x +if [ -f "../../../../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../../../../techlibs/common + TECHLIBS_PREFIX=../../../../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" done +for t in *_tb.v; do + echo "all:: run-$t" + echo "run-$t:" + echo " @echo 'Running $t..'" + echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v" + echo " @if ! vvp -N ${t%_tb.v}_testbench > ${t%_tb.v}_testbench.log 2>&1; then grep 'ERROR' ${t%_tb.v}_testbench.log; exit 0; elif grep 'ERROR' ${t%_tb.v}_testbench.log || ! grep 'OKAY' ${t%_tb.v}_testbench.log; then echo "FAIL"; exit 0; fi" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ice40/temp/.gitignore b/tests/ice40/temp/.gitignore deleted file mode 100644 index 397b4a762..000000000 --- a/tests/ice40/temp/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.log diff --git a/tests/ice40/tribuf.v b/tests/ice40/tribuf.v index b2b5e37d6..870a02584 100644 --- a/tests/ice40/tribuf.v +++ b/tests/ice40/tribuf.v @@ -1,10 +1,10 @@ module tristate (en, i, o); input en; input i; - output reg o; + output o; + + assign o = en ? i : 1'bz; - always @(en or i) - o <= (en)? i : 1'bZ; endmodule diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index b319e6622..9b7ea1eab 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -1,6 +1,8 @@ -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 -design -load postopt -select -assert-count 1 t:SB_LUT4 -select -assert-count 1 t:SB_CARRY +read_verilog tribuf.v +hierarchy -top top +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D From c5754d9e8bed8d9238a462712f39a8d818401ad3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:17:25 -0700 Subject: [PATCH 05/43] Make multiplier wider, do not do tech independent synth --- tests/ice40/mul.v | 7 +++---- tests/ice40/mul.ys | 7 +++---- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/tests/ice40/mul.v b/tests/ice40/mul.v index c099db0d9..d5b48b1d7 100644 --- a/tests/ice40/mul.v +++ b/tests/ice40/mul.v @@ -1,10 +1,9 @@ module top ( - input [3:0] x, - input [3:0] y, + input [5:0] x, + input [5:0] y, - output [3:0] A, - output [3:0] B + output [11:0] A, ); assign A = x * y; diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys index 35048d14a..adf1b3211 100644 --- a/tests/ice40/mul.ys +++ b/tests/ice40/mul.ys @@ -1,9 +1,8 @@ read_verilog mul.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +#synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 15 t:SB_LUT4 -select -assert-count 3 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D From 9e537a76b5a0487e0788054091132d2fd7f1a0dd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:20:18 -0700 Subject: [PATCH 06/43] Move $dffe to dffs.{v,ys} --- tests/ice40/adffs.v | 10 ---------- tests/ice40/adffs.ys | 9 ++++++--- tests/ice40/dffs.v | 34 +++++++++++++++++++++++++++++++++- tests/ice40/dffs.ys | 6 ++---- 4 files changed, 41 insertions(+), 18 deletions(-) diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index af7022c79..972184cfa 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -22,16 +22,6 @@ module adffn q <= d; endmodule -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - module dffsr ( input d, clk, pre, clr, output reg q ); initial begin diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index aee8cd6b4..d58ce1a82 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,8 +1,11 @@ read_verilog adffs.v proc -dff2dffe -synth_ice40 -select -assert-count 2 t:SB_DFFR +async2sync +synth -flatten -run coarse # technology-independent coarse grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFF select -assert-count 1 t:SB_DFFE select -assert-count 4 t:SB_LUT4 #select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v index d57c8c97c..d97840c43 100644 --- a/tests/ice40/dffs.v +++ b/tests/ice40/dffs.v @@ -1,5 +1,37 @@ -module top +module dff ( input d, clk, output reg q ); always @( posedge clk ) q <= d; endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index 0fa0bc3eb..ddd8e5734 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,11 +1,9 @@ read_verilog dffs.v -proc -flatten -dff2dffe hierarchy -top top synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF -select -assert-none t:SB_DFF %% t:* %D +select -assert-count 1 t:SB_DFFE +select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D From 388eb3288c907dbc8b2763ffc20b0b5fccba81ed Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:21:54 -0700 Subject: [PATCH 07/43] Remove dffe instantation --- tests/ice40/adffs.v | 7 ------- 1 file changed, 7 deletions(-) diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index 972184cfa..e09ef52e1 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -88,11 +88,4 @@ adffn u_adffn ( .q (b3 ) ); -dffe u_dffe ( - .clk (clk ), - .en (clr), - .d (a ), - .q (b4 ) - ); - endmodule From 9224b3bc1721ae45abf11594b3ab9a58e50aa86f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:30:49 -0700 Subject: [PATCH 08/43] Remove tech independent synthesis --- tests/ice40/add_sub.ys | 1 - tests/ice40/adffs.ys | 10 +++++----- tests/ice40/dffs.ys | 3 ++- tests/ice40/div_mod.ys | 2 +- tests/ice40/latches.ys | 5 +++-- tests/ice40/memory.ys | 1 + tests/ice40/mul.ys | 1 - tests/ice40/mux.ys | 8 +++++--- tests/ice40/tribuf.ys | 5 +++-- 9 files changed, 20 insertions(+), 16 deletions(-) diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index 84f31ec53..8eeb221db 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,6 +1,5 @@ read_verilog add_sub.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index d58ce1a82..3c676e590 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,12 +1,12 @@ read_verilog adffs.v proc async2sync -synth -flatten -run coarse # technology-independent coarse grained synthesis +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFE -select -assert-count 4 t:SB_LUT4 -#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D -write_verilog adffs_synth.v +select -assert-count 1 t:SB_DFFN +select -assert-count 2 t:SB_DFFSR +select -assert-count 7 t:SB_LUT4 +select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index ddd8e5734..b14346f5a 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -1,6 +1,7 @@ read_verilog dffs.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +proc +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 93285cede..613cad760 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,6 +1,6 @@ read_verilog div_mod.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index 0abd7f195..fe0d1f70e 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,5 +1,6 @@ read_verilog latches.v synth_ice40 -select -assert-count 5 t:SB_LUT4 -#select -assert-none t:SB_LUT4 %% t:* %D +cd top +select -assert-count 4 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D write_verilog latches_synth.v diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index a0391e93d..0a8c48dca 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,4 +1,5 @@ read_verilog memory.v synth_ice40 +cd top select -assert-count 1 t:SB_RAM40_4K write_verilog memory_synth.v diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys index adf1b3211..aec7d0b1f 100644 --- a/tests/ice40/mul.ys +++ b/tests/ice40/mul.ys @@ -1,6 +1,5 @@ read_verilog mul.v hierarchy -top top -#synth -flatten -run coarse # technology-independent coarse grained synthesis equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 9e3d87b7f..63d22001f 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,6 +1,8 @@ read_verilog mux.v -synth_ice40 +proc +flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 design -load postopt -select -assert-count 20 t:SB_LUT4 -select -assert-count 1 t:SB_CARRY +cd top +select -assert-count 19 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index 9b7ea1eab..8049a37ab 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -1,7 +1,8 @@ read_verilog tribuf.v hierarchy -top top -synth -flatten -run coarse # technology-independent coarse grained synthesis -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ From f9906eed68beab359ed83beee2bcf42ffac908c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:35:35 -0700 Subject: [PATCH 09/43] Fix comments --- tests/ice40/add_sub.ys | 2 +- tests/ice40/adffs.ys | 4 ++-- tests/ice40/dffs.ys | 2 +- tests/ice40/div_mod.ys | 2 +- tests/ice40/memory.ys | 1 + tests/ice40/mul.ys | 2 +- tests/ice40/mux.ys | 6 +++--- tests/ice40/tribuf.ys | 2 +- 8 files changed, 11 insertions(+), 10 deletions(-) diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys index 8eeb221db..4a998d98d 100644 --- a/tests/ice40/add_sub.ys +++ b/tests/ice40/add_sub.ys @@ -1,6 +1,6 @@ read_verilog add_sub.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 11 t:SB_LUT4 diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys index 3c676e590..14b251c5c 100644 --- a/tests/ice40/adffs.ys +++ b/tests/ice40/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v proc -async2sync +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys index b14346f5a..ee7f884b1 100644 --- a/tests/ice40/dffs.ys +++ b/tests/ice40/dffs.ys @@ -2,7 +2,7 @@ read_verilog dffs.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 613cad760..96753b4ef 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -1,7 +1,7 @@ read_verilog div_mod.v hierarchy -top top flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 88 t:SB_LUT4 diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index 0a8c48dca..fa5d004b0 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -2,4 +2,5 @@ read_verilog memory.v synth_ice40 cd top select -assert-count 1 t:SB_RAM40_4K +select -assert-none t:SB_RAM40_4K %% t:* %D write_verilog memory_synth.v diff --git a/tests/ice40/mul.ys b/tests/ice40/mul.ys index aec7d0b1f..8a0822a84 100644 --- a/tests/ice40/mul.ys +++ b/tests/ice40/mul.ys @@ -1,6 +1,6 @@ read_verilog mul.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_MAC16 diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys index 63d22001f..182b49499 100644 --- a/tests/ice40/mux.ys +++ b/tests/ice40/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -design -load postopt -cd top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module select -assert-count 19 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index 8049a37ab..ef4266959 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -2,7 +2,7 @@ read_verilog tribuf.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ From 61087329efcfac45de6b69ded33f38c8f8817eef Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 12:36:27 -0700 Subject: [PATCH 10/43] Fix tribuf test --- tests/ice40/tribuf.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys index ef4266959..d1e1b3108 100644 --- a/tests/ice40/tribuf.ys +++ b/tests/ice40/tribuf.ys @@ -2,7 +2,7 @@ read_verilog tribuf.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ From 659a481482b59efd672034bff9e034fa6d47336c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 13:57:11 -0700 Subject: [PATCH 11/43] Remove unused output --- tests/ice40/adffs.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v index e09ef52e1..93c8bf52c 100644 --- a/tests/ice40/adffs.v +++ b/tests/ice40/adffs.v @@ -55,7 +55,7 @@ input clk, input clr, input pre, input a, -output b,b1,b2,b3,b4 +output b,b1,b2,b3 ); dffsr u_dffsr ( From 8e3754bdb468842a784ef5eac8427a59055673c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 13:57:19 -0700 Subject: [PATCH 12/43] Hide tri-state warning message for now --- tests/ice40/.gitignore | 1 + tests/ice40/run-test.sh | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore index 397b4a762..1d329c933 100644 --- a/tests/ice40/.gitignore +++ b/tests/ice40/.gitignore @@ -1 +1,2 @@ *.log +/run-test.mk diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 5bd9fb173..184d8f09b 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -12,7 +12,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" done for t in *_tb.v; do echo "all:: run-$t" From 5061d239ae2d6881b898662f838a0f4cfc24ca88 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 14:03:02 -0700 Subject: [PATCH 13/43] Fail if iverilog fails --- tests/ice40/run-test.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 184d8f09b..90a8a3c83 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -18,8 +18,8 @@ for t in *_tb.v; do echo "all:: run-$t" echo "run-$t:" echo " @echo 'Running $t..'" - echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v" - echo " @if ! vvp -N ${t%_tb.v}_testbench > ${t%_tb.v}_testbench.log 2>&1; then grep 'ERROR' ${t%_tb.v}_testbench.log; exit 0; elif grep 'ERROR' ${t%_tb.v}_testbench.log || ! grep 'OKAY' ${t%_tb.v}_testbench.log; then echo "FAIL"; exit 0; fi" + echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" + echo " @vvp -N ${t%_tb.v}_testbench" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then From 65e6c23abd9add59b95a024c91d4fff6d15ba135 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 14:20:03 -0700 Subject: [PATCH 14/43] Spelling --- passes/equiv/equiv_make.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index dbd8682e6..4855ce29e 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -532,10 +532,10 @@ struct EquivMakePass : public Pass { log_cmd_error("Equiv module %s already exists.\n", args[argidx+2].c_str()); if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes()) - log_cmd_error("Gold module contains memories or procresses. Run 'memory' or 'proc' respectively.\n"); + log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n"); if (worker.gate_mod->has_memories() || worker.gate_mod->has_processes()) - log_cmd_error("Gate module contains memories or procresses. Run 'memory' or 'proc' respectively.\n"); + log_cmd_error("Gate module contains memories or processes. Run 'memory' or 'proc' respectively.\n"); worker.read_blacklists(); worker.read_encfiles(); From 43e7c4917ad42b01d34b496c35798416a050aa61 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 15:50:38 -0700 Subject: [PATCH 15/43] Do not print OKAY --- tests/ice40/latches_tb.v | 2 -- tests/ice40/memory_tb.v | 2 -- 2 files changed, 4 deletions(-) diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v index 47ae8670c..b0585264b 100644 --- a/tests/ice40/latches_tb.v +++ b/tests/ice40/latches_tb.v @@ -10,8 +10,6 @@ module testbench; #5 clk = 1; #5 clk = 0; end - - $display("OKAY"); end diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v index 5905f3ddd..be69374eb 100644 --- a/tests/ice40/memory_tb.v +++ b/tests/ice40/memory_tb.v @@ -10,8 +10,6 @@ module testbench; #5 clk = 1; #5 clk = 0; end - - $display("OKAY"); end From 698a0e3aafcae48535c68996fccf002c0e0e3aea Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 15:50:45 -0700 Subject: [PATCH 16/43] WIP for equivalency checking memories --- tests/ice40/memory.ys | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index fa5d004b0..9b7490cd8 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -1,5 +1,17 @@ read_verilog memory.v -synth_ice40 +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D From 36cf0a3dd5a9599b60eb449a2401454e7a7af6fd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 22 Aug 2019 16:50:14 -0700 Subject: [PATCH 17/43] Remove adffs_tb.v --- tests/ice40/adffs_tb.v | 75 ------------------------------------------ 1 file changed, 75 deletions(-) delete mode 100644 tests/ice40/adffs_tb.v diff --git a/tests/ice40/adffs_tb.v b/tests/ice40/adffs_tb.v deleted file mode 100644 index e049edabc..000000000 --- a/tests/ice40/adffs_tb.v +++ /dev/null @@ -1,75 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - - $display("OKAY"); - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2,doutB3,doutB4; - reg dff,ndff,adff,adffn,dffe = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @( posedge clk, posedge dinA[1], posedge dinA[2] ) - if ( dinA[2] ) - dff <= 1'b0; - else if ( dinA[1] ) - dff <= 1'b1; - else - dff <= dinA[0]; - - always @( negedge clk, negedge dinA[1], negedge dinA[2] ) - if ( !dinA[2] ) - ndff <= 1'b0; - else if ( !dinA[1] ) - ndff <= 1'b1; - else - ndff <= dinA[0]; - - always @( posedge clk, posedge dinA[2] ) - if ( dinA[2] ) - adff <= 1'b0; - else - adff <= dinA[0]; - - always @( posedge clk, negedge dinA[2] ) - if ( !dinA[2] ) - adffn <= 1'b0; - else - adffn <= dinA[0]; - - always @( posedge clk ) - if ( dinA[2] ) - dffe <= dinA[0]; - - assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff)); - assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff)); - assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff)); - //assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn)); - //assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe)); - -endmodule From 0b25dbf1c6107fc993ab3c88b82c3e33f0bbd516 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 23 Aug 2019 12:40:14 +0300 Subject: [PATCH 18/43] Fix path in run-test.sh --- tests/ice40/run-test.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 90a8a3c83..ddd6d349f 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -1,7 +1,7 @@ set -e -if [ -f "../../../../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../../../../techlibs/common - TECHLIBS_PREFIX=../../../../../techlibs +if [ -f "../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../techlibs/common + TECHLIBS_PREFIX=../../techlibs else COMMON_PREFIX=/usr/local/share/yosys TECHLIBS_PREFIX=/usr/local/share/yosys From 3c10f58d043432197fdf5169404710f8ab68db8c Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 23 Aug 2019 17:00:16 +0300 Subject: [PATCH 19/43] Fix run-test.sh; Add new test for dpram. --- tests/ice40/dpram.v | 20 ++++++++++ tests/ice40/dpram.ys | 18 +++++++++ tests/ice40/dpram_tb.v | 81 +++++++++++++++++++++++++++++++++++++++++ tests/ice40/run-test.sh | 2 +- 4 files changed, 120 insertions(+), 1 deletion(-) create mode 100644 tests/ice40/dpram.v create mode 100644 tests/ice40/dpram.ys create mode 100644 tests/ice40/dpram_tb.v diff --git a/tests/ice40/dpram.v b/tests/ice40/dpram.v new file mode 100644 index 000000000..2e69d6b3b --- /dev/null +++ b/tests/ice40/dpram.v @@ -0,0 +1,20 @@ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + reg [7:0] mem [(1<<8)-1:0]; + + always @(posedge clk) // Write memory. + begin + if (we_a) + mem[addr_a] <= data_a; // Using write address bus. + end + always @(posedge clk) // Read memory. + begin + pq_a <= mem[addr_b]; // Using read address bus. + end + + top uut ( + .din(data_a), + .write_en(we_a), + .waddr(addr_a), + .wclk(clk), + .raddr(addr_b), + .rclk(clk), + .dout(q_a) + ); + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index ddd6d349f..75aa08339 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -16,7 +16,7 @@ for x in *.ys; do done for t in *_tb.v; do echo "all:: run-$t" - echo "run-$t:" + echo "run-$t: ${t%_tb.v}_synth.v" echo " @echo 'Running $t..'" echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" echo " @vvp -N ${t%_tb.v}_testbench" From c29380b381b68396342990822c63c36381f3ee3a Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 23 Aug 2019 18:55:01 +0300 Subject: [PATCH 20/43] Fix pull request --- tests/ice40/.gitignore | 2 ++ tests/ice40/run-test.sh | 14 +++++++------- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore index 1d329c933..9a71dca69 100644 --- a/tests/ice40/.gitignore +++ b/tests/ice40/.gitignore @@ -1,2 +1,4 @@ *.log /run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 75aa08339..bd9d35314 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -13,14 +13,14 @@ for x in *.ys; do echo "run-$x:" echo " @echo 'Running $x..'" echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + + if [ -f "${x%.ys}_tb.v" ]; then + echo " @echo 'Running ${x%.ys}_tb.v..'" + echo " @iverilog -o ${x%.ys}_testbench $t ${x%.ys}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" + echo " @vvp -N ${x%.ys}_testbench" + fi done -for t in *_tb.v; do - echo "all:: run-$t" - echo "run-$t: ${t%_tb.v}_synth.v" - echo " @echo 'Running $t..'" - echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" - echo " @vvp -N ${t%_tb.v}_testbench" -done + for s in *.sh; do if [ "$s" != "run-test.sh" ]; then echo "all:: run-$s" From aad9bad32604645e2d61f0858234a1838e8b88eb Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 27 Aug 2019 13:56:26 +0300 Subject: [PATCH 21/43] Add tests for macc and rom; Test cases from https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071; In both cases synthesized only LUTs and DFFs. --- tests/ice40/macc.v | 22 ++++++++++++++++++++++ tests/ice40/macc.ys | 10 ++++++++++ tests/ice40/rom.v | 15 +++++++++++++++ tests/ice40/rom.ys | 8 ++++++++ 4 files changed, 55 insertions(+) create mode 100644 tests/ice40/macc.v create mode 100644 tests/ice40/macc.ys create mode 100644 tests/ice40/rom.v create mode 100644 tests/ice40/rom.ys diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v new file mode 100644 index 000000000..115f8ce42 --- /dev/null +++ b/tests/ice40/macc.v @@ -0,0 +1,22 @@ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys new file mode 100644 index 000000000..233e7e890 --- /dev/null +++ b/tests/ice40/macc.ys @@ -0,0 +1,10 @@ +read_verilog macc.v +proc +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 41 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-count 7 t:SB_DFFSR +select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D diff --git a/tests/ice40/rom.v b/tests/ice40/rom.v new file mode 100644 index 000000000..c31ca3b2b --- /dev/null +++ b/tests/ice40/rom.v @@ -0,0 +1,15 @@ +module top(data, addr); +output [3:0] data; +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/ice40/rom.ys b/tests/ice40/rom.ys new file mode 100644 index 000000000..41d214e2a --- /dev/null +++ b/tests/ice40/rom.ys @@ -0,0 +1,8 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 5 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D From 134d3fea909bae02f4f814e3d649658502b44b73 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 27 Aug 2019 18:12:18 +0300 Subject: [PATCH 22/43] Add tests for ecp5 architecture. --- Makefile | 1 + tests/ecp5/.gitignore | 4 ++ tests/ecp5/add_sub.v | 13 ++++++ tests/ecp5/add_sub.ys | 8 ++++ tests/ecp5/adffs.v | 91 ++++++++++++++++++++++++++++++++++++ tests/ecp5/adffs.ys | 12 +++++ tests/ecp5/common.v | 47 +++++++++++++++++++ tests/ecp5/dffs.v | 37 +++++++++++++++ tests/ecp5/dffs.ys | 10 ++++ tests/ecp5/div_mod.v | 13 ++++++ tests/ecp5/div_mod.ys | 12 +++++ tests/ecp5/dpram.v | 20 ++++++++ tests/ecp5/dpram.ys | 18 ++++++++ tests/ecp5/dpram_tb.v | 81 ++++++++++++++++++++++++++++++++ tests/ecp5/latches.v | 58 +++++++++++++++++++++++ tests/ecp5/latches.ys | 7 +++ tests/ecp5/latches_tb.v | 57 +++++++++++++++++++++++ tests/ecp5/macc.v | 22 +++++++++ tests/ecp5/macc.ys | 10 ++++ tests/ecp5/memory.v | 21 +++++++++ tests/ecp5/memory.ys | 22 +++++++++ tests/ecp5/memory_tb.v | 79 +++++++++++++++++++++++++++++++ tests/ecp5/mul.v | 11 +++++ tests/ecp5/mul.ys | 11 +++++ tests/ecp5/mux.v | 100 ++++++++++++++++++++++++++++++++++++++++ tests/ecp5/mux.ys | 11 +++++ tests/ecp5/rom.v | 15 ++++++ tests/ecp5/rom.ys | 9 ++++ tests/ecp5/run-test.sh | 33 +++++++++++++ tests/ecp5/tribuf.v | 23 +++++++++ tests/ecp5/tribuf.ys | 9 ++++ 31 files changed, 865 insertions(+) create mode 100644 tests/ecp5/.gitignore create mode 100644 tests/ecp5/add_sub.v create mode 100644 tests/ecp5/add_sub.ys create mode 100644 tests/ecp5/adffs.v create mode 100644 tests/ecp5/adffs.ys create mode 100644 tests/ecp5/common.v create mode 100644 tests/ecp5/dffs.v create mode 100644 tests/ecp5/dffs.ys create mode 100644 tests/ecp5/div_mod.v create mode 100644 tests/ecp5/div_mod.ys create mode 100644 tests/ecp5/dpram.v create mode 100644 tests/ecp5/dpram.ys create mode 100644 tests/ecp5/dpram_tb.v create mode 100644 tests/ecp5/latches.v create mode 100644 tests/ecp5/latches.ys create mode 100644 tests/ecp5/latches_tb.v create mode 100644 tests/ecp5/macc.v create mode 100644 tests/ecp5/macc.ys create mode 100644 tests/ecp5/memory.v create mode 100644 tests/ecp5/memory.ys create mode 100644 tests/ecp5/memory_tb.v create mode 100644 tests/ecp5/mul.v create mode 100644 tests/ecp5/mul.ys create mode 100644 tests/ecp5/mux.v create mode 100644 tests/ecp5/mux.ys create mode 100644 tests/ecp5/rom.v create mode 100644 tests/ecp5/rom.ys create mode 100755 tests/ecp5/run-test.sh create mode 100644 tests/ecp5/tribuf.v create mode 100644 tests/ecp5/tribuf.ys diff --git a/Makefile b/Makefile index 9cfa6a0de..d94ab2465 100644 --- a/Makefile +++ b/Makefile @@ -700,6 +700,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..5829fef5f --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,12 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFN +select -assert-count 2 t:DFFSR +select -assert-count 7 t:LUT4 +select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ecp5/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..07470c5ba --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFE +select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..169c5978e --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 45 t:L6MUX21 +select -assert-count 183 t:LUT4 +select -assert-count 79 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..2e69d6b3b --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,20 @@ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + reg [7:0] mem [(1<<8)-1:0]; + + always @(posedge clk) // Write memory. + begin + if (we_a) + mem[addr_a] <= data_a; // Using write address bus. + end + always @(posedge clk) // Read memory. + begin + pq_a <= mem[addr_b]; // Using read address bus. + end + + top uut ( + .din(data_a), + .write_en(we_a), + .waddr(addr_a), + .wclk(clk), + .raddr(addr_b), + .rclk(clk), + .dout(q_a) + ); + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ecp5/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys new file mode 100644 index 000000000..2c77304a1 --- /dev/null +++ b/tests/ecp5/latches.ys @@ -0,0 +1,7 @@ +read_verilog latches.v +synth_ecp5 +cd top +select -assert-count 4 t:LUT4 +select -assert-count 1 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D +write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v new file mode 100644 index 000000000..b0585264b --- /dev/null +++ b/tests/ecp5/latches_tb.v @@ -0,0 +1,57 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v new file mode 100644 index 000000000..115f8ce42 --- /dev/null +++ b/tests/ecp5/macc.v @@ -0,0 +1,22 @@ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys new file mode 100644 index 000000000..530877727 --- /dev/null +++ b/tests/ecp5/macc.ys @@ -0,0 +1,10 @@ +read_verilog macc.v +proc +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 41 t:LUT4 +select -assert-count 6 t:CARRY +select -assert-count 7 t:DFFSR +select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ecp5/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys new file mode 100644 index 000000000..9fdeb0d16 --- /dev/null +++ b/tests/ecp5/memory.ys @@ -0,0 +1,22 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D +write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v new file mode 100644 index 000000000..be69374eb --- /dev/null +++ b/tests/ecp5/memory_tb.v @@ -0,0 +1,79 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/ecp5/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys new file mode 100644 index 000000000..0e8d6908f --- /dev/null +++ b/tests/ecp5/mul.ys @@ -0,0 +1,11 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:CCU2C +select -assert-count 46 t:L6MUX21 +select -assert-count 169 t:LUT4 +select -assert-count 72 t:PFUMX + +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ecp5/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys new file mode 100644 index 000000000..47a965dd3 --- /dev/null +++ b/tests/ecp5/mux.ys @@ -0,0 +1,11 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 30 t:LUT4 +select -assert-count 7 t:L6MUX21 +select -assert-count 12 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v new file mode 100644 index 000000000..c31ca3b2b --- /dev/null +++ b/tests/ecp5/rom.v @@ -0,0 +1,15 @@ +module top(data, addr); +output [3:0] data; +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys new file mode 100644 index 000000000..8a52749a1 --- /dev/null +++ b/tests/ecp5/rom.ys @@ -0,0 +1,9 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:LUT4 +select -assert-count 3 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh new file mode 100755 index 000000000..bd9d35314 --- /dev/null +++ b/tests/ecp5/run-test.sh @@ -0,0 +1,33 @@ +set -e +if [ -f "../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../techlibs/common + TECHLIBS_PREFIX=../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + + if [ -f "${x%.ys}_tb.v" ]; then + echo " @echo 'Running ${x%.ys}_tb.v..'" + echo " @iverilog -o ${x%.ys}_testbench $t ${x%.ys}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" + echo " @vvp -N ${x%.ys}_testbench" + fi +done + +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D From 980830f7b82f2a974f43580f61e917f99fbb4e7e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 27 Aug 2019 18:28:05 +0300 Subject: [PATCH 23/43] Revert "Add tests for ecp5 architecture." This reverts commit 134d3fea909bae02f4f814e3d649658502b44b73. --- Makefile | 1 - tests/ecp5/.gitignore | 4 -- tests/ecp5/add_sub.v | 13 ------ tests/ecp5/add_sub.ys | 8 ---- tests/ecp5/adffs.v | 91 ------------------------------------ tests/ecp5/adffs.ys | 12 ----- tests/ecp5/common.v | 47 ------------------- tests/ecp5/dffs.v | 37 --------------- tests/ecp5/dffs.ys | 10 ---- tests/ecp5/div_mod.v | 13 ------ tests/ecp5/div_mod.ys | 12 ----- tests/ecp5/dpram.v | 20 -------- tests/ecp5/dpram.ys | 18 -------- tests/ecp5/dpram_tb.v | 81 -------------------------------- tests/ecp5/latches.v | 58 ----------------------- tests/ecp5/latches.ys | 7 --- tests/ecp5/latches_tb.v | 57 ----------------------- tests/ecp5/macc.v | 22 --------- tests/ecp5/macc.ys | 10 ---- tests/ecp5/memory.v | 21 --------- tests/ecp5/memory.ys | 22 --------- tests/ecp5/memory_tb.v | 79 ------------------------------- tests/ecp5/mul.v | 11 ----- tests/ecp5/mul.ys | 11 ----- tests/ecp5/mux.v | 100 ---------------------------------------- tests/ecp5/mux.ys | 11 ----- tests/ecp5/rom.v | 15 ------ tests/ecp5/rom.ys | 9 ---- tests/ecp5/run-test.sh | 33 ------------- tests/ecp5/tribuf.v | 23 --------- tests/ecp5/tribuf.ys | 9 ---- 31 files changed, 865 deletions(-) delete mode 100644 tests/ecp5/.gitignore delete mode 100644 tests/ecp5/add_sub.v delete mode 100644 tests/ecp5/add_sub.ys delete mode 100644 tests/ecp5/adffs.v delete mode 100644 tests/ecp5/adffs.ys delete mode 100644 tests/ecp5/common.v delete mode 100644 tests/ecp5/dffs.v delete mode 100644 tests/ecp5/dffs.ys delete mode 100644 tests/ecp5/div_mod.v delete mode 100644 tests/ecp5/div_mod.ys delete mode 100644 tests/ecp5/dpram.v delete mode 100644 tests/ecp5/dpram.ys delete mode 100644 tests/ecp5/dpram_tb.v delete mode 100644 tests/ecp5/latches.v delete mode 100644 tests/ecp5/latches.ys delete mode 100644 tests/ecp5/latches_tb.v delete mode 100644 tests/ecp5/macc.v delete mode 100644 tests/ecp5/macc.ys delete mode 100644 tests/ecp5/memory.v delete mode 100644 tests/ecp5/memory.ys delete mode 100644 tests/ecp5/memory_tb.v delete mode 100644 tests/ecp5/mul.v delete mode 100644 tests/ecp5/mul.ys delete mode 100644 tests/ecp5/mux.v delete mode 100644 tests/ecp5/mux.ys delete mode 100644 tests/ecp5/rom.v delete mode 100644 tests/ecp5/rom.ys delete mode 100755 tests/ecp5/run-test.sh delete mode 100644 tests/ecp5/tribuf.v delete mode 100644 tests/ecp5/tribuf.ys diff --git a/Makefile b/Makefile index d94ab2465..9cfa6a0de 100644 --- a/Makefile +++ b/Makefile @@ -700,7 +700,6 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) - +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore deleted file mode 100644 index 9a71dca69..000000000 --- a/tests/ecp5/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.log -/run-test.mk -+*_synth.v -+*_testbench diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ecp5/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys deleted file mode 100644 index 03aec6694..000000000 --- a/tests/ecp5/add_sub.ys +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 %% t:* %D - diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v deleted file mode 100644 index 93c8bf52c..000000000 --- a/tests/ecp5/adffs.v +++ /dev/null @@ -1,91 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffsr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnsnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffsr u_dffsr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnsnr u_ndffnsnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys deleted file mode 100644 index 5829fef5f..000000000 --- a/tests/ecp5/adffs.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog adffs.v -proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DFF -select -assert-count 1 t:DFFN -select -assert-count 2 t:DFFSR -select -assert-count 7 t:LUT4 -select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v deleted file mode 100644 index 5446f0817..000000000 --- a/tests/ecp5/common.v +++ /dev/null @@ -1,47 +0,0 @@ -module assert_dff(input clk, input test, input pat); - always @(posedge clk) - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time); - $stop; - end - end -endmodule - -module assert_tri(input en, input A, input B); - always @(posedge en) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule - -module assert_Z(input clk, input A); - always @(posedge clk) - begin - #1; - if (A === 1'bZ) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); - $stop; - end - end -endmodule - -module assert_comb(input A, input B); - always @(*) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/ecp5/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys deleted file mode 100644 index 07470c5ba..000000000 --- a/tests/ecp5/dffs.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog dffs.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DFF -select -assert-count 1 t:DFFE -select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ecp5/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys deleted file mode 100644 index 169c5978e..000000000 --- a/tests/ecp5/div_mod.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 28 t:CCU2C -select -assert-count 45 t:L6MUX21 -select -assert-count 183 t:LUT4 -select -assert-count 79 t:PFUMX -select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v deleted file mode 100644 index 2e69d6b3b..000000000 --- a/tests/ecp5/dpram.v +++ /dev/null @@ -1,20 +0,0 @@ -module top (din, write_en, waddr, wclk, raddr, rclk, dout); -parameter addr_width = 8; -parameter data_width = 8; -input [addr_width-1:0] waddr, raddr; -input [data_width-1:0] din; -input write_en, wclk, rclk; -output [data_width-1:0] dout; -reg [data_width-1:0] dout; -reg [data_width-1:0] mem [(1< 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - reg [7:0] mem [(1<<8)-1:0]; - - always @(posedge clk) // Write memory. - begin - if (we_a) - mem[addr_a] <= data_a; // Using write address bus. - end - always @(posedge clk) // Read memory. - begin - pq_a <= mem[addr_b]; // Using read address bus. - end - - top uut ( - .din(data_a), - .write_en(we_a), - .waddr(addr_a), - .wclk(clk), - .raddr(addr_b), - .rclk(clk), - .dout(q_a) - ); - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v deleted file mode 100644 index 9dc43e4c2..000000000 --- a/tests/ecp5/latches.v +++ /dev/null @@ -1,58 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys deleted file mode 100644 index 2c77304a1..000000000 --- a/tests/ecp5/latches.ys +++ /dev/null @@ -1,7 +0,0 @@ -read_verilog latches.v -synth_ecp5 -cd top -select -assert-count 4 t:LUT4 -select -assert-count 1 t:PFUMX -select -assert-none t:LUT4 t:PFUMX %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v deleted file mode 100644 index b0585264b..000000000 --- a/tests/ecp5/latches_tb.v +++ /dev/null @@ -1,57 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2; - reg lat,latn,latsr = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @* - if ( clk ) - lat <= dinA[0]; - - - always @* - if ( !clk ) - latn <= dinA[0]; - - - always @* - if ( dinA[2] ) - latsr <= 1'b0; - else if ( dinA[1] ) - latsr <= 1'b1; - else if ( clk ) - latsr <= dinA[0]; - - assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); - assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); - assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); - -endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v deleted file mode 100644 index 115f8ce42..000000000 --- a/tests/ecp5/macc.v +++ /dev/null @@ -1,22 +0,0 @@ -module top(clk,a,b,c,set); -parameter A_WIDTH = 4; -parameter B_WIDTH = 3; -input set; -input clk; -input signed [(A_WIDTH - 1):0] a; -input signed [(B_WIDTH - 1):0] b; -output signed [(A_WIDTH + B_WIDTH - 1):0] c; -reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; -assign c = reg_tmp_c; -always @(posedge clk) -begin -if(set) -begin -reg_tmp_c <= 0; -end -else -begin -reg_tmp_c <= a * b + c; -end -end -endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys deleted file mode 100644 index 530877727..000000000 --- a/tests/ecp5/macc.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog macc.v -proc -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 41 t:LUT4 -select -assert-count 6 t:CARRY -select -assert-count 7 t:DFFSR -select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/ecp5/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys deleted file mode 100644 index 9fdeb0d16..000000000 --- a/tests/ecp5/memory.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 24 t:L6MUX21 -select -assert-count 71 t:LUT4 -select -assert-count 32 t:PFUMX -select -assert-count 8 t:TRELLIS_DPR16X4 -select -assert-count 35 t:TRELLIS_FF -select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v deleted file mode 100644 index be69374eb..000000000 --- a/tests/ecp5/memory_tb.v +++ /dev/null @@ -1,79 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [7:0] data_a = 0; - reg [5:0] addr_a = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - top uut ( - .data_a(data_a), - .addr_a(addr_a), - .we_a(we_a), - .clk(clk), - .q_a(q_a) - ); - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - // Declare the RAM variable for check - reg [7:0] ram[63:0]; - - // Port A for check - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - pq_a <= data_a; - end - pq_a <= ram[addr_a]; - end - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/ecp5/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys deleted file mode 100644 index 0e8d6908f..000000000 --- a/tests/ecp5/mul.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mul.v -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:CCU2C -select -assert-count 46 t:L6MUX21 -select -assert-count 169 t:LUT4 -select -assert-count 72 t:PFUMX - -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v deleted file mode 100644 index 0814b733e..000000000 --- a/tests/ecp5/mux.v +++ /dev/null @@ -1,100 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys deleted file mode 100644 index 47a965dd3..000000000 --- a/tests/ecp5/mux.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mux.v -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 30 t:LUT4 -select -assert-count 7 t:L6MUX21 -select -assert-count 12 t:PFUMX - -select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v deleted file mode 100644 index c31ca3b2b..000000000 --- a/tests/ecp5/rom.v +++ /dev/null @@ -1,15 +0,0 @@ -module top(data, addr); -output [3:0] data; -input [4:0] addr; -always @(addr) begin -case (addr) -0 : data = 'h4; -1 : data = 'h9; -2 : data = 'h1; -15 : data = 'h8; -16 : data = 'h1; -17 : data = 'h0; -default : data = 'h0; -endcase -end -endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys deleted file mode 100644 index 8a52749a1..000000000 --- a/tests/ecp5/rom.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog rom.v -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:LUT4 -select -assert-count 3 t:PFUMX -select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh deleted file mode 100755 index bd9d35314..000000000 --- a/tests/ecp5/run-test.sh +++ /dev/null @@ -1,33 +0,0 @@ -set -e -if [ -f "../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../techlibs/common - TECHLIBS_PREFIX=../../techlibs -else - COMMON_PREFIX=/usr/local/share/yosys - TECHLIBS_PREFIX=/usr/local/share/yosys -fi -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" - - if [ -f "${x%.ys}_tb.v" ]; then - echo " @echo 'Running ${x%.ys}_tb.v..'" - echo " @iverilog -o ${x%.ys}_testbench $t ${x%.ys}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" - echo " @vvp -N ${x%.ys}_testbench" - fi -done - -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/ecp5/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys deleted file mode 100644 index f454a0c02..000000000 --- a/tests/ecp5/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D From 2270ead09fb4695442c66fe5c06445235f390f2b Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 28 Aug 2019 09:47:03 +0300 Subject: [PATCH 24/43] Add tests for ecp5 --- Makefile | 1 + tests/ecp5/.gitignore | 2 + tests/ecp5/add_sub.v | 13 ++++++ tests/ecp5/add_sub.ys | 8 ++++ tests/ecp5/adffs.v | 91 ++++++++++++++++++++++++++++++++++++ tests/ecp5/adffs.ys | 12 +++++ tests/ecp5/common.v | 47 +++++++++++++++++++ tests/ecp5/dffs.v | 37 +++++++++++++++ tests/ecp5/dffs.ys | 10 ++++ tests/ecp5/div_mod.v | 13 ++++++ tests/ecp5/div_mod.ys | 12 +++++ tests/ecp5/dpram.v | 20 ++++++++ tests/ecp5/dpram.ys | 18 ++++++++ tests/ecp5/dpram_tb.v | 81 ++++++++++++++++++++++++++++++++ tests/ecp5/latches.v | 58 +++++++++++++++++++++++ tests/ecp5/latches.ys | 7 +++ tests/ecp5/latches_tb.v | 57 +++++++++++++++++++++++ tests/ecp5/macc.v | 22 +++++++++ tests/ecp5/macc.ys | 10 ++++ tests/ecp5/memory.v | 21 +++++++++ tests/ecp5/memory.ys | 22 +++++++++ tests/ecp5/memory_tb.v | 79 +++++++++++++++++++++++++++++++ tests/ecp5/mul.v | 11 +++++ tests/ecp5/mul.ys | 11 +++++ tests/ecp5/mux.v | 100 ++++++++++++++++++++++++++++++++++++++++ tests/ecp5/mux.ys | 11 +++++ tests/ecp5/rom.v | 15 ++++++ tests/ecp5/rom.ys | 9 ++++ tests/ecp5/run-test.sh | 33 +++++++++++++ tests/ecp5/tribuf.v | 23 +++++++++ tests/ecp5/tribuf.ys | 9 ++++ 31 files changed, 863 insertions(+) create mode 100644 tests/ecp5/.gitignore create mode 100644 tests/ecp5/add_sub.v create mode 100644 tests/ecp5/add_sub.ys create mode 100644 tests/ecp5/adffs.v create mode 100644 tests/ecp5/adffs.ys create mode 100644 tests/ecp5/common.v create mode 100644 tests/ecp5/dffs.v create mode 100644 tests/ecp5/dffs.ys create mode 100644 tests/ecp5/div_mod.v create mode 100644 tests/ecp5/div_mod.ys create mode 100644 tests/ecp5/dpram.v create mode 100644 tests/ecp5/dpram.ys create mode 100644 tests/ecp5/dpram_tb.v create mode 100644 tests/ecp5/latches.v create mode 100644 tests/ecp5/latches.ys create mode 100644 tests/ecp5/latches_tb.v create mode 100644 tests/ecp5/macc.v create mode 100644 tests/ecp5/macc.ys create mode 100644 tests/ecp5/memory.v create mode 100644 tests/ecp5/memory.ys create mode 100644 tests/ecp5/memory_tb.v create mode 100644 tests/ecp5/mul.v create mode 100644 tests/ecp5/mul.ys create mode 100644 tests/ecp5/mux.v create mode 100644 tests/ecp5/mux.ys create mode 100644 tests/ecp5/rom.v create mode 100644 tests/ecp5/rom.ys create mode 100755 tests/ecp5/run-test.sh create mode 100644 tests/ecp5/tribuf.v create mode 100644 tests/ecp5/tribuf.ys diff --git a/Makefile b/Makefile index 9cfa6a0de..d94ab2465 100644 --- a/Makefile +++ b/Makefile @@ -700,6 +700,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..5829fef5f --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,12 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFN +select -assert-count 2 t:DFFSR +select -assert-count 7 t:LUT4 +select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v new file mode 100644 index 000000000..5446f0817 --- /dev/null +++ b/tests/ecp5/common.v @@ -0,0 +1,47 @@ +module assert_dff(input clk, input test, input pat); + always @(posedge clk) + begin + #1; + if (test != pat) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time); + $stop; + end + end +endmodule + +module assert_tri(input en, input A, input B); + always @(posedge en) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule + +module assert_Z(input clk, input A); + always @(posedge clk) + begin + #1; + if (A === 1'bZ) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); + $stop; + end + end +endmodule + +module assert_comb(input A, input B); + always @(*) + begin + #1; + if (A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..07470c5ba --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFE +select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..169c5978e --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 45 t:L6MUX21 +select -assert-count 183 t:LUT4 +select -assert-count 79 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..2e69d6b3b --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,20 @@ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + reg [7:0] mem [(1<<8)-1:0]; + + always @(posedge clk) // Write memory. + begin + if (we_a) + mem[addr_a] <= data_a; // Using write address bus. + end + always @(posedge clk) // Read memory. + begin + pq_a <= mem[addr_b]; // Using read address bus. + end + + top uut ( + .din(data_a), + .write_en(we_a), + .waddr(addr_a), + .wclk(clk), + .raddr(addr_b), + .rclk(clk), + .dout(q_a) + ); + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ecp5/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys new file mode 100644 index 000000000..2c77304a1 --- /dev/null +++ b/tests/ecp5/latches.ys @@ -0,0 +1,7 @@ +read_verilog latches.v +synth_ecp5 +cd top +select -assert-count 4 t:LUT4 +select -assert-count 1 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D +write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v new file mode 100644 index 000000000..b0585264b --- /dev/null +++ b/tests/ecp5/latches_tb.v @@ -0,0 +1,57 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [2:0] dinA = 0; + wire doutB,doutB1,doutB2; + reg lat,latn,latsr = 0; + + top uut ( + .clk (clk ), + .a (dinA[0] ), + .pre (dinA[1] ), + .clr (dinA[2] ), + .b (doutB ), + .b1 (doutB1 ), + .b2 (doutB2 ) + ); + + always @(posedge clk) begin + #3; + dinA <= dinA + 1; + end + + always @* + if ( clk ) + lat <= dinA[0]; + + + always @* + if ( !clk ) + latn <= dinA[0]; + + + always @* + if ( dinA[2] ) + latsr <= 1'b0; + else if ( dinA[1] ) + latsr <= 1'b1; + else if ( clk ) + latsr <= dinA[0]; + + assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); + assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); + assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); + +endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v new file mode 100644 index 000000000..115f8ce42 --- /dev/null +++ b/tests/ecp5/macc.v @@ -0,0 +1,22 @@ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys new file mode 100644 index 000000000..530877727 --- /dev/null +++ b/tests/ecp5/macc.ys @@ -0,0 +1,10 @@ +read_verilog macc.v +proc +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 41 t:LUT4 +select -assert-count 6 t:CARRY +select -assert-count 7 t:DFFSR +select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ecp5/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys new file mode 100644 index 000000000..9fdeb0d16 --- /dev/null +++ b/tests/ecp5/memory.ys @@ -0,0 +1,22 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D +write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v new file mode 100644 index 000000000..be69374eb --- /dev/null +++ b/tests/ecp5/memory_tb.v @@ -0,0 +1,79 @@ +module testbench; + reg clk; + + initial begin + // $dumpfile("testbench.vcd"); + // $dumpvars(0, testbench); + + #5 clk = 0; + repeat (10000) begin + #5 clk = 1; + #5 clk = 0; + end + end + + + reg [7:0] data_a = 0; + reg [5:0] addr_a = 0; + reg we_a = 0; + reg re_a = 1; + wire [7:0] q_a; + reg mem_init = 0; + + reg [7:0] pq_a; + + top uut ( + .data_a(data_a), + .addr_a(addr_a), + .we_a(we_a), + .clk(clk), + .q_a(q_a) + ); + + always @(posedge clk) begin + #3; + data_a <= data_a + 17; + + addr_a <= addr_a + 1; + end + + always @(posedge addr_a) begin + #10; + if(addr_a > 6'h3E) + mem_init <= 1; + end + + always @(posedge clk) begin + //#3; + we_a <= !we_a; + end + + // Declare the RAM variable for check + reg [7:0] ram[63:0]; + + // Port A for check + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + pq_a <= data_a; + end + pq_a <= ram[addr_a]; + end + + uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); + +endmodule + +module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); + always @(posedge clk) + begin + #1; + if (en == 1 & init == 1 & A !== B) + begin + $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); + $stop; + end + end +endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/ecp5/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys new file mode 100644 index 000000000..0e8d6908f --- /dev/null +++ b/tests/ecp5/mul.ys @@ -0,0 +1,11 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:CCU2C +select -assert-count 46 t:L6MUX21 +select -assert-count 169 t:LUT4 +select -assert-count 72 t:PFUMX + +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ecp5/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys new file mode 100644 index 000000000..47a965dd3 --- /dev/null +++ b/tests/ecp5/mux.ys @@ -0,0 +1,11 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 30 t:LUT4 +select -assert-count 7 t:L6MUX21 +select -assert-count 12 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v new file mode 100644 index 000000000..c31ca3b2b --- /dev/null +++ b/tests/ecp5/rom.v @@ -0,0 +1,15 @@ +module top(data, addr); +output [3:0] data; +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys new file mode 100644 index 000000000..8a52749a1 --- /dev/null +++ b/tests/ecp5/rom.ys @@ -0,0 +1,9 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:LUT4 +select -assert-count 3 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh new file mode 100755 index 000000000..22c495784 --- /dev/null +++ b/tests/ecp5/run-test.sh @@ -0,0 +1,33 @@ +set -e +if [ -f "../../techlibs/common/simcells.v" ]; then + COMMON_PREFIX=../../techlibs/common + TECHLIBS_PREFIX=../../techlibs +else + COMMON_PREFIX=/usr/local/share/yosys + TECHLIBS_PREFIX=/usr/local/share/yosys +fi +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" +done +for t in *_tb.v; do + echo "all:: run-$t" + echo "run-$t: ${t%_tb.v}_synth.v" + echo " @echo 'Running $t..'" + echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ecp5/cells_sim.v" + echo " @vvp -N ${t%_tb.v}_testbench" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D From fe58790f3789a79b867660031d7e3e28cb3fff20 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 28 Aug 2019 09:49:58 +0300 Subject: [PATCH 25/43] Revert "Add tests for ecp5" This reverts commit 2270ead09fb4695442c66fe5c06445235f390f2b. --- Makefile | 1 - tests/ecp5/.gitignore | 2 - tests/ecp5/add_sub.v | 13 ------ tests/ecp5/add_sub.ys | 8 ---- tests/ecp5/adffs.v | 91 ------------------------------------ tests/ecp5/adffs.ys | 12 ----- tests/ecp5/common.v | 47 ------------------- tests/ecp5/dffs.v | 37 --------------- tests/ecp5/dffs.ys | 10 ---- tests/ecp5/div_mod.v | 13 ------ tests/ecp5/div_mod.ys | 12 ----- tests/ecp5/dpram.v | 20 -------- tests/ecp5/dpram.ys | 18 -------- tests/ecp5/dpram_tb.v | 81 -------------------------------- tests/ecp5/latches.v | 58 ----------------------- tests/ecp5/latches.ys | 7 --- tests/ecp5/latches_tb.v | 57 ----------------------- tests/ecp5/macc.v | 22 --------- tests/ecp5/macc.ys | 10 ---- tests/ecp5/memory.v | 21 --------- tests/ecp5/memory.ys | 22 --------- tests/ecp5/memory_tb.v | 79 ------------------------------- tests/ecp5/mul.v | 11 ----- tests/ecp5/mul.ys | 11 ----- tests/ecp5/mux.v | 100 ---------------------------------------- tests/ecp5/mux.ys | 11 ----- tests/ecp5/rom.v | 15 ------ tests/ecp5/rom.ys | 9 ---- tests/ecp5/run-test.sh | 33 ------------- tests/ecp5/tribuf.v | 23 --------- tests/ecp5/tribuf.ys | 9 ---- 31 files changed, 863 deletions(-) delete mode 100644 tests/ecp5/.gitignore delete mode 100644 tests/ecp5/add_sub.v delete mode 100644 tests/ecp5/add_sub.ys delete mode 100644 tests/ecp5/adffs.v delete mode 100644 tests/ecp5/adffs.ys delete mode 100644 tests/ecp5/common.v delete mode 100644 tests/ecp5/dffs.v delete mode 100644 tests/ecp5/dffs.ys delete mode 100644 tests/ecp5/div_mod.v delete mode 100644 tests/ecp5/div_mod.ys delete mode 100644 tests/ecp5/dpram.v delete mode 100644 tests/ecp5/dpram.ys delete mode 100644 tests/ecp5/dpram_tb.v delete mode 100644 tests/ecp5/latches.v delete mode 100644 tests/ecp5/latches.ys delete mode 100644 tests/ecp5/latches_tb.v delete mode 100644 tests/ecp5/macc.v delete mode 100644 tests/ecp5/macc.ys delete mode 100644 tests/ecp5/memory.v delete mode 100644 tests/ecp5/memory.ys delete mode 100644 tests/ecp5/memory_tb.v delete mode 100644 tests/ecp5/mul.v delete mode 100644 tests/ecp5/mul.ys delete mode 100644 tests/ecp5/mux.v delete mode 100644 tests/ecp5/mux.ys delete mode 100644 tests/ecp5/rom.v delete mode 100644 tests/ecp5/rom.ys delete mode 100755 tests/ecp5/run-test.sh delete mode 100644 tests/ecp5/tribuf.v delete mode 100644 tests/ecp5/tribuf.ys diff --git a/Makefile b/Makefile index d94ab2465..9cfa6a0de 100644 --- a/Makefile +++ b/Makefile @@ -700,7 +700,6 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) - +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore deleted file mode 100644 index 1d329c933..000000000 --- a/tests/ecp5/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ecp5/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys deleted file mode 100644 index 03aec6694..000000000 --- a/tests/ecp5/add_sub.ys +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 %% t:* %D - diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v deleted file mode 100644 index 93c8bf52c..000000000 --- a/tests/ecp5/adffs.v +++ /dev/null @@ -1,91 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffsr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnsnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre, negedge clr ) - if ( !clr ) - q <= 1'b0; - else if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffsr u_dffsr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnsnr u_ndffnsnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys deleted file mode 100644 index 5829fef5f..000000000 --- a/tests/ecp5/adffs.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog adffs.v -proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DFF -select -assert-count 1 t:DFFN -select -assert-count 2 t:DFFSR -select -assert-count 7 t:LUT4 -select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D diff --git a/tests/ecp5/common.v b/tests/ecp5/common.v deleted file mode 100644 index 5446f0817..000000000 --- a/tests/ecp5/common.v +++ /dev/null @@ -1,47 +0,0 @@ -module assert_dff(input clk, input test, input pat); - always @(posedge clk) - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time); - $stop; - end - end -endmodule - -module assert_tri(input en, input A, input B); - always @(posedge en) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule - -module assert_Z(input clk, input A); - always @(posedge clk) - begin - #1; - if (A === 1'bZ) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); - $stop; - end - end -endmodule - -module assert_comb(input A, input B); - always @(*) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/ecp5/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys deleted file mode 100644 index 07470c5ba..000000000 --- a/tests/ecp5/dffs.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog dffs.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:DFF -select -assert-count 1 t:DFFE -select -assert-none t:DFF t:DFFE %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ecp5/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys deleted file mode 100644 index 169c5978e..000000000 --- a/tests/ecp5/div_mod.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 28 t:CCU2C -select -assert-count 45 t:L6MUX21 -select -assert-count 183 t:LUT4 -select -assert-count 79 t:PFUMX -select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v deleted file mode 100644 index 2e69d6b3b..000000000 --- a/tests/ecp5/dpram.v +++ /dev/null @@ -1,20 +0,0 @@ -module top (din, write_en, waddr, wclk, raddr, rclk, dout); -parameter addr_width = 8; -parameter data_width = 8; -input [addr_width-1:0] waddr, raddr; -input [data_width-1:0] din; -input write_en, wclk, rclk; -output [data_width-1:0] dout; -reg [data_width-1:0] dout; -reg [data_width-1:0] mem [(1< 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - reg [7:0] mem [(1<<8)-1:0]; - - always @(posedge clk) // Write memory. - begin - if (we_a) - mem[addr_a] <= data_a; // Using write address bus. - end - always @(posedge clk) // Read memory. - begin - pq_a <= mem[addr_b]; // Using read address bus. - end - - top uut ( - .din(data_a), - .write_en(we_a), - .waddr(addr_a), - .wclk(clk), - .raddr(addr_b), - .rclk(clk), - .dout(q_a) - ); - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v deleted file mode 100644 index 9dc43e4c2..000000000 --- a/tests/ecp5/latches.v +++ /dev/null @@ -1,58 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys deleted file mode 100644 index 2c77304a1..000000000 --- a/tests/ecp5/latches.ys +++ /dev/null @@ -1,7 +0,0 @@ -read_verilog latches.v -synth_ecp5 -cd top -select -assert-count 4 t:LUT4 -select -assert-count 1 t:PFUMX -select -assert-none t:LUT4 t:PFUMX %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ecp5/latches_tb.v b/tests/ecp5/latches_tb.v deleted file mode 100644 index b0585264b..000000000 --- a/tests/ecp5/latches_tb.v +++ /dev/null @@ -1,57 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2; - reg lat,latn,latsr = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @* - if ( clk ) - lat <= dinA[0]; - - - always @* - if ( !clk ) - latn <= dinA[0]; - - - always @* - if ( dinA[2] ) - latsr <= 1'b0; - else if ( dinA[1] ) - latsr <= 1'b1; - else if ( clk ) - latsr <= dinA[0]; - - assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); - assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); - assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); - -endmodule diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v deleted file mode 100644 index 115f8ce42..000000000 --- a/tests/ecp5/macc.v +++ /dev/null @@ -1,22 +0,0 @@ -module top(clk,a,b,c,set); -parameter A_WIDTH = 4; -parameter B_WIDTH = 3; -input set; -input clk; -input signed [(A_WIDTH - 1):0] a; -input signed [(B_WIDTH - 1):0] b; -output signed [(A_WIDTH + B_WIDTH - 1):0] c; -reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; -assign c = reg_tmp_c; -always @(posedge clk) -begin -if(set) -begin -reg_tmp_c <= 0; -end -else -begin -reg_tmp_c <= a * b + c; -end -end -endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys deleted file mode 100644 index 530877727..000000000 --- a/tests/ecp5/macc.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog macc.v -proc -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 41 t:LUT4 -select -assert-count 6 t:CARRY -select -assert-count 7 t:DFFSR -select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/ecp5/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys deleted file mode 100644 index 9fdeb0d16..000000000 --- a/tests/ecp5/memory.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 24 t:L6MUX21 -select -assert-count 71 t:LUT4 -select -assert-count 32 t:PFUMX -select -assert-count 8 t:TRELLIS_DPR16X4 -select -assert-count 35 t:TRELLIS_FF -select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ecp5/memory_tb.v b/tests/ecp5/memory_tb.v deleted file mode 100644 index be69374eb..000000000 --- a/tests/ecp5/memory_tb.v +++ /dev/null @@ -1,79 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [7:0] data_a = 0; - reg [5:0] addr_a = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - top uut ( - .data_a(data_a), - .addr_a(addr_a), - .we_a(we_a), - .clk(clk), - .q_a(q_a) - ); - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - // Declare the RAM variable for check - reg [7:0] ram[63:0]; - - // Port A for check - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - pq_a <= data_a; - end - pq_a <= ram[addr_a]; - end - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/ecp5/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys deleted file mode 100644 index 0e8d6908f..000000000 --- a/tests/ecp5/mul.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mul.v -hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:CCU2C -select -assert-count 46 t:L6MUX21 -select -assert-count 169 t:LUT4 -select -assert-count 72 t:PFUMX - -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v deleted file mode 100644 index 0814b733e..000000000 --- a/tests/ecp5/mux.v +++ /dev/null @@ -1,100 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys deleted file mode 100644 index 47a965dd3..000000000 --- a/tests/ecp5/mux.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mux.v -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 30 t:LUT4 -select -assert-count 7 t:L6MUX21 -select -assert-count 12 t:PFUMX - -select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v deleted file mode 100644 index c31ca3b2b..000000000 --- a/tests/ecp5/rom.v +++ /dev/null @@ -1,15 +0,0 @@ -module top(data, addr); -output [3:0] data; -input [4:0] addr; -always @(addr) begin -case (addr) -0 : data = 'h4; -1 : data = 'h9; -2 : data = 'h1; -15 : data = 'h8; -16 : data = 'h1; -17 : data = 'h0; -default : data = 'h0; -endcase -end -endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys deleted file mode 100644 index 8a52749a1..000000000 --- a/tests/ecp5/rom.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog rom.v -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:LUT4 -select -assert-count 3 t:PFUMX -select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh deleted file mode 100755 index 22c495784..000000000 --- a/tests/ecp5/run-test.sh +++ /dev/null @@ -1,33 +0,0 @@ -set -e -if [ -f "../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../techlibs/common - TECHLIBS_PREFIX=../../techlibs -else - COMMON_PREFIX=/usr/local/share/yosys - TECHLIBS_PREFIX=/usr/local/share/yosys -fi -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" -done -for t in *_tb.v; do - echo "all:: run-$t" - echo "run-$t: ${t%_tb.v}_synth.v" - echo " @echo 'Running $t..'" - echo " @iverilog -o ${t%_tb.v}_testbench $t ${t%_tb.v}_synth.v common.v $TECHLIBS_PREFIX/ecp5/cells_sim.v" - echo " @vvp -N ${t%_tb.v}_testbench" -done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/ecp5/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys deleted file mode 100644 index f454a0c02..000000000 --- a/tests/ecp5/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D From ebd0a1875b74460da10d9b114e97c1468d8542db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 12:21:15 -0700 Subject: [PATCH 26/43] Use equiv_opt for latches --- tests/ice40/latches.ys | 11 +++++++- tests/ice40/latches_tb.v | 57 ---------------------------------------- 2 files changed, 10 insertions(+), 58 deletions(-) delete mode 100644 tests/ice40/latches_tb.v diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index fe0d1f70e..f3562559e 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,6 +1,15 @@ read_verilog latches.v +design -save read + +proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock +flatten +synth_ice40 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read synth_ice40 cd top select -assert-count 4 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ice40/latches_tb.v b/tests/ice40/latches_tb.v deleted file mode 100644 index b0585264b..000000000 --- a/tests/ice40/latches_tb.v +++ /dev/null @@ -1,57 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [2:0] dinA = 0; - wire doutB,doutB1,doutB2; - reg lat,latn,latsr = 0; - - top uut ( - .clk (clk ), - .a (dinA[0] ), - .pre (dinA[1] ), - .clr (dinA[2] ), - .b (doutB ), - .b1 (doutB1 ), - .b2 (doutB2 ) - ); - - always @(posedge clk) begin - #3; - dinA <= dinA + 1; - end - - always @* - if ( clk ) - lat <= dinA[0]; - - - always @* - if ( !clk ) - latn <= dinA[0]; - - - always @* - if ( dinA[2] ) - latsr <= 1'b0; - else if ( dinA[1] ) - latsr <= 1'b1; - else if ( clk ) - latsr <= dinA[0]; - - assert_dff lat_test(.clk(clk), .test(doutB), .pat(lat)); - assert_dff latn_test(.clk(clk), .test(doutB1), .pat(latn)); - assert_dff latsr_test(.clk(clk), .test(doutB2), .pat(latsr)); - -endmodule From 87d5d9b8c80df696c836831df9d9eff6f20476fa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 12:30:35 -0700 Subject: [PATCH 27/43] Use equiv for memory and dpram --- tests/ice40/dpram.ys | 5 +-- tests/ice40/dpram_tb.v | 81 ----------------------------------------- tests/ice40/memory.ys | 5 +-- tests/ice40/memory_tb.v | 79 ---------------------------------------- 4 files changed, 2 insertions(+), 168 deletions(-) delete mode 100644 tests/ice40/dpram_tb.v delete mode 100644 tests/ice40/memory_tb.v diff --git a/tests/ice40/dpram.ys b/tests/ice40/dpram.ys index 77364e5ae..4f6a253ea 100644 --- a/tests/ice40/dpram.ys +++ b/tests/ice40/dpram.ys @@ -6,13 +6,10 @@ equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 memory opt -full -# TODO -#equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D -write_verilog dpram_synth.v diff --git a/tests/ice40/dpram_tb.v b/tests/ice40/dpram_tb.v deleted file mode 100644 index dede64614..000000000 --- a/tests/ice40/dpram_tb.v +++ /dev/null @@ -1,81 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [7:0] data_a = 0; - reg [7:0] addr_a = 0; - reg [7:0] addr_b = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - addr_b <= addr_b + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - reg [7:0] mem [(1<<8)-1:0]; - - always @(posedge clk) // Write memory. - begin - if (we_a) - mem[addr_a] <= data_a; // Using write address bus. - end - always @(posedge clk) // Read memory. - begin - pq_a <= mem[addr_b]; // Using read address bus. - end - - top uut ( - .din(data_a), - .write_en(we_a), - .waddr(addr_a), - .wclk(clk), - .raddr(addr_b), - .rclk(clk), - .dout(q_a) - ); - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule diff --git a/tests/ice40/memory.ys b/tests/ice40/memory.ys index 9b7490cd8..a66afbae6 100644 --- a/tests/ice40/memory.ys +++ b/tests/ice40/memory.ys @@ -6,13 +6,10 @@ equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 memory opt -full -# TODO -#equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ice40/memory_tb.v b/tests/ice40/memory_tb.v deleted file mode 100644 index be69374eb..000000000 --- a/tests/ice40/memory_tb.v +++ /dev/null @@ -1,79 +0,0 @@ -module testbench; - reg clk; - - initial begin - // $dumpfile("testbench.vcd"); - // $dumpvars(0, testbench); - - #5 clk = 0; - repeat (10000) begin - #5 clk = 1; - #5 clk = 0; - end - end - - - reg [7:0] data_a = 0; - reg [5:0] addr_a = 0; - reg we_a = 0; - reg re_a = 1; - wire [7:0] q_a; - reg mem_init = 0; - - reg [7:0] pq_a; - - top uut ( - .data_a(data_a), - .addr_a(addr_a), - .we_a(we_a), - .clk(clk), - .q_a(q_a) - ); - - always @(posedge clk) begin - #3; - data_a <= data_a + 17; - - addr_a <= addr_a + 1; - end - - always @(posedge addr_a) begin - #10; - if(addr_a > 6'h3E) - mem_init <= 1; - end - - always @(posedge clk) begin - //#3; - we_a <= !we_a; - end - - // Declare the RAM variable for check - reg [7:0] ram[63:0]; - - // Port A for check - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - pq_a <= data_a; - end - pq_a <= ram[addr_a]; - end - - uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a), .B(pq_a)); - -endmodule - -module uut_mem_checker(input clk, input init, input en, input [7:0] A, input [7:0] B); - always @(posedge clk) - begin - #1; - if (en == 1 & init == 1 & A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule From b8a9f73089234ed699a4057b50fd739a90abea43 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 12:36:20 -0700 Subject: [PATCH 28/43] Comment out *.sh used for testbenches as we have no more --- tests/ice40/run-test.sh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index bd9d35314..941dcaecd 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -21,13 +21,13 @@ for x in *.ys; do fi done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done +#for s in *.sh; do +# if [ "$s" != "run-test.sh" ]; then +# echo "all:: run-$s" +# echo "run-$s:" +# echo " @echo 'Running $s..'" +# echo " @bash $s" +# fi +#done } > run-test.mk exec ${MAKE:-make} -f run-test.mk From d588c6898fb7cfebe52a71a48d6fb21d1623e61b Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Thu, 29 Aug 2019 10:49:46 +0300 Subject: [PATCH 29/43] Add comments for examples from Lattice user guide --- tests/ice40/dpram.v | 3 +++ tests/ice40/macc.v | 3 +++ tests/ice40/rom.v | 3 +++ 3 files changed, 9 insertions(+) diff --git a/tests/ice40/dpram.v b/tests/ice40/dpram.v index 2e69d6b3b..3ea4c1f27 100644 --- a/tests/ice40/dpram.v +++ b/tests/ice40/dpram.v @@ -1,3 +1,6 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ module top (din, write_en, waddr, wclk, raddr, rclk, dout); parameter addr_width = 8; parameter data_width = 8; diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v index 115f8ce42..63a3d3a74 100644 --- a/tests/ice40/macc.v +++ b/tests/ice40/macc.v @@ -1,3 +1,6 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77]. +*/ module top(clk,a,b,c,set); parameter A_WIDTH = 4; parameter B_WIDTH = 3; diff --git a/tests/ice40/rom.v b/tests/ice40/rom.v index c31ca3b2b..0a0f41f37 100644 --- a/tests/ice40/rom.v +++ b/tests/ice40/rom.v @@ -1,3 +1,6 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. +*/ module top(data, addr); output [3:0] data; input [4:0] addr; From 3e0f73c3df3119a839b326464a8399ce4256edc7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 12:12:59 -0700 Subject: [PATCH 30/43] abc9 to not call "clean" at end of run (often called outside) --- passes/techmap/abc9.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 84cb2c04f..f2662e0cb 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1300,9 +1300,6 @@ struct Abc9Pass : public Pass { assign_map.clear(); - // The "clean" pass also contains a design->check() call - Pass::call(design, "clean"); - log_pop(); } } Abc9Pass; From c52db44f9ab19194dbdefd35bd697ab99650f510 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 12:13:52 -0700 Subject: [PATCH 31/43] Group abc_* attribute doc with other attributes --- README.md | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/README.md b/README.md index 38ca77862..95dc01aa8 100644 --- a/README.md +++ b/README.md @@ -347,6 +347,23 @@ Verilog Attributes and non-standard features it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. +- The module attribute ``abc_box_id`` specifies a positive integer linking a + blackbox or whitebox definition to a corresponding entry in a `abc9` + box-file. + +- The port attribute ``abc_scc_break`` indicates a module input port that will + be treated as a primary output during `abc9` techmapping. Doing so eliminates + the possibility of a strongly-connected component (i.e. a combinatorial loop) + existing. Typically, this is specified for sequential inputs on otherwise + combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D` + port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths + as a combinatorial loop. + +- The port attribute ``abc_carry`` marks the carry-in (if an input port) and + carry-out (if output port) ports of a box. This information is necessary for + `abc9` to preserve the integrity of carry-chains. Specifying this attribute + onto a bus port will affect only its most significant bit. + - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset @@ -423,23 +440,6 @@ Verilog Attributes and non-standard features blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this functionality. (By default specify .. endspecify blocks are ignored.) -- The module attribute ``abc_box_id`` specifies a positive integer linking a - blackbox or whitebox definition to a corresponding entry in a `abc9` - box-file. - -- The port attribute ``abc_scc_break`` indicates a module input port that will - be treated as a primary output during `abc9` techmapping. Doing so eliminates - the possibility of a strongly-connected component (i.e. a combinatorial loop) - existing. Typically, this is specified for sequential inputs on otherwise - combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D` - port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths - as a combinatorial loop. - -- The port attribute ``abc_carry`` marks the carry-in (if an input port) and - carry-out (if output port) ports of a box. This information is necessary for - `abc9` to preserve the integrity of carry-chains. Specifying this attribute - onto a bus port will affect only its most significant bit. - Non-standard or SystemVerilog features for formal verification ============================================================== From 18cabe9370c46b72e9fb52eb9be5a7c7fb873274 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 17:24:03 -0700 Subject: [PATCH 32/43] Output has priority over input when stitching in abc9 --- passes/techmap/abc9.cc | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f2662e0cb..6fdf987f0 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -694,30 +694,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module - for (auto &it : mapped_mod->wires_) { - RTLIL::Wire *w = it.second; - if (!w->port_input && !w->port_output) - continue; - RTLIL::Wire *wire = module->wire(w->name); + for (auto port : mapped_mod->ports) { + RTLIL::Wire *w = mapped_mod->wire(port); + RTLIL::Wire *wire = module->wire(port); log_assert(wire); - RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); + RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); - log_assert(w->port_input || w->port_output); RTLIL::SigSig conn; - if (w->port_input) { - conn.first = remap_wire; - conn.second = signal; - in_wires++; - module->connect(conn); - } if (w->port_output) { conn.first = signal; conn.second = remap_wire; out_wires++; module->connect(conn); } + else if (w->port_input) { + conn.first = remap_wire; + conn.second = signal; + in_wires++; + module->connect(conn); + } } for (auto &it : bit_users) From 5d16bf831688ff665b0ec2abd6835b71320b2db5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 17:24:25 -0700 Subject: [PATCH 33/43] parse_xaiger() to do "clean -purge" --- frontends/aiger/aigerparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 06522939f..2e1fb8fad 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -974,7 +974,7 @@ void AigerReader::post_process() // operate (and run checks on) this one module RTLIL::Design *mapped_design = new RTLIL::Design; mapped_design->add(module); - Pass::call(mapped_design, "clean"); + Pass::call(mapped_design, "clean -purge"); mapped_design->modules_.erase(module->name); delete mapped_design; From 6a111ad32487fb49c5d30db5697c794814ffa511 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 29 Aug 2019 17:24:48 -0700 Subject: [PATCH 34/43] Nicer formatting --- tests/simple_abc9/run-test.sh | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 49ae23338..8df6994e3 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -20,4 +20,10 @@ fi cp ../simple/*.v . cp ../simple/*.sv . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\ + hierarchy; \ + synth -run coarse; \ + opt -full; \ + techmap; abc9 -lut 4 -box ../abc.box; \ + check -assert; \ + select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" From 20f4aea480e259272360f4c77667a9e1828986e8 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 08:53:35 +0300 Subject: [PATCH 35/43] Remove simulation from run-test.sh --- tests/ice40/run-test.sh | 6 ------ 1 file changed, 6 deletions(-) diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index 941dcaecd..acfd582d2 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -13,12 +13,6 @@ for x in *.ys; do echo "run-$x:" echo " @echo 'Running $x..'" echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" - - if [ -f "${x%.ys}_tb.v" ]; then - echo " @echo 'Running ${x%.ys}_tb.v..'" - echo " @iverilog -o ${x%.ys}_testbench $t ${x%.ys}_synth.v common.v $TECHLIBS_PREFIX/ice40/cells_sim.v" - echo " @vvp -N ${x%.ys}_testbench" - fi done #for s in *.sh; do From 8e3abda19308bd4ac7e03d38f899831e853f4794 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 09:11:03 +0300 Subject: [PATCH 36/43] Remove simulation from run-test.sh (unnecessary paths) --- tests/ice40/run-test.sh | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh index acfd582d2..2c72ca3a9 100755 --- a/tests/ice40/run-test.sh +++ b/tests/ice40/run-test.sh @@ -1,11 +1,5 @@ +#!/usr/bin/env bash set -e -if [ -f "../../techlibs/common/simcells.v" ]; then - COMMON_PREFIX=../../techlibs/common - TECHLIBS_PREFIX=../../techlibs -else - COMMON_PREFIX=/usr/local/share/yosys - TECHLIBS_PREFIX=/usr/local/share/yosys -fi { echo "all::" for x in *.ys; do @@ -14,14 +8,13 @@ for x in *.ys; do echo " @echo 'Running $x..'" echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" done - -#for s in *.sh; do -# if [ "$s" != "run-test.sh" ]; then -# echo "all:: run-$s" -# echo "run-$s:" -# echo " @echo 'Running $s..'" -# echo " @bash $s" -# fi -#done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done } > run-test.mk exec ${MAKE:-make} -f run-test.mk From eb0a5b2293d005d3a6a2d680b40f1449a489204d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 09:17:32 +0300 Subject: [PATCH 37/43] Remove unnecessary common.v(assertions for testbenches). --- tests/ice40/common.v | 47 -------------------------------------------- 1 file changed, 47 deletions(-) delete mode 100644 tests/ice40/common.v diff --git a/tests/ice40/common.v b/tests/ice40/common.v deleted file mode 100644 index 5446f0817..000000000 --- a/tests/ice40/common.v +++ /dev/null @@ -1,47 +0,0 @@ -module assert_dff(input clk, input test, input pat); - always @(posedge clk) - begin - #1; - if (test != pat) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time); - $stop; - end - end -endmodule - -module assert_tri(input en, input A, input B); - always @(posedge en) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule - -module assert_Z(input clk, input A); - always @(posedge clk) - begin - #1; - if (A === 1'bZ) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A); - $stop; - end - end -endmodule - -module assert_comb(input A, input B); - always @(*) - begin - #1; - if (A !== B) - begin - $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B); - $stop; - end - end -endmodule From d144748401df3f6d527771e6d30cc1eb1e08734e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 09:45:33 +0300 Subject: [PATCH 38/43] Add new tests. --- tests/ice40/alu.v | 19 +++++++++++ tests/ice40/alu.ys | 11 +++++++ tests/ice40/counter.v | 17 ++++++++++ tests/ice40/counter.ys | 11 +++++++ tests/ice40/fsm.v | 73 ++++++++++++++++++++++++++++++++++++++++++ tests/ice40/fsm.ys | 13 ++++++++ tests/ice40/logic.v | 18 +++++++++++ tests/ice40/logic.ys | 7 ++++ tests/ice40/shifter.v | 22 +++++++++++++ tests/ice40/shifter.ys | 9 ++++++ 10 files changed, 200 insertions(+) create mode 100644 tests/ice40/alu.v create mode 100644 tests/ice40/alu.ys create mode 100644 tests/ice40/counter.v create mode 100644 tests/ice40/counter.ys create mode 100644 tests/ice40/fsm.v create mode 100644 tests/ice40/fsm.ys create mode 100644 tests/ice40/logic.v create mode 100644 tests/ice40/logic.ys create mode 100644 tests/ice40/shifter.v create mode 100644 tests/ice40/shifter.ys diff --git a/tests/ice40/alu.v b/tests/ice40/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/ice40/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/ice40/alu.ys b/tests/ice40/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/ice40/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/ice40/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys new file mode 100644 index 000000000..fb32e67a5 --- /dev/null +++ b/tests/ice40/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 7 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/fsm.v b/tests/ice40/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/ice40/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/ice40/fsm.ys b/tests/ice40/fsm.ys new file mode 100644 index 000000000..4cc8629d6 --- /dev/null +++ b/tests/ice40/fsm.ys @@ -0,0 +1,13 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 2 t:SB_DFFESR +select -assert-count 2 t:SB_DFFSR +select -assert-count 1 t:SB_DFFSS +select -assert-count 13 t:SB_LUT4 +select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/logic.v b/tests/ice40/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/ice40/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/ice40/logic.ys b/tests/ice40/logic.ys new file mode 100644 index 000000000..fc5e5b1d8 --- /dev/null +++ b/tests/ice40/logic.ys @@ -0,0 +1,7 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/shifter.v b/tests/ice40/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/ice40/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/ice40/shifter.ys b/tests/ice40/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/ice40/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D From 86f1375ecd3e6721a0e5da469672db890926914e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 12:38:28 +0300 Subject: [PATCH 39/43] Fix test for counter --- tests/ice40/counter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys index fb32e67a5..c65c21622 100644 --- a/tests/ice40/counter.ys +++ b/tests/ice40/counter.ys @@ -5,7 +5,7 @@ flatten equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 7 t:SB_CARRY +select -assert-count 6 t:SB_CARRY select -assert-count 8 t:SB_DFFR select -assert-count 8 t:SB_LUT4 select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D From f4a48ce8e6785fe9828b8896b9a60a74580dc2eb Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 13:22:11 +0300 Subject: [PATCH 40/43] fix div_mod test --- tests/ice40/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 96753b4ef..f55490572 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -4,6 +4,6 @@ flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 88 t:SB_LUT4 +select -assert-count 62 t:SB_LUT4 select -assert-count 65 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D From 94a56c14b78a2872d65bb30371151e934a259275 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 14:17:03 +0300 Subject: [PATCH 41/43] div_mod test fix --- tests/ice40/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index f55490572..21cac7144 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -5,5 +5,5 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 62 t:SB_LUT4 -select -assert-count 65 t:SB_CARRY +select -assert-count 41 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D From 17c92dc679458a9ffabd76e2ce8e2491bd249110 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 15:22:46 +0300 Subject: [PATCH 42/43] Fix macc test --- tests/ice40/macc.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index 233e7e890..d65c31b73 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -4,7 +4,7 @@ hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 41 t:SB_LUT4 +select -assert-count 38 t:SB_LUT4 select -assert-count 6 t:SB_CARRY select -assert-count 7 t:SB_DFFSR select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D From 53912ad649d6e9f447b9e4037255606783a0cf51 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Fri, 30 Aug 2019 16:01:36 +0300 Subject: [PATCH 43/43] macc test fix --- tests/ice40/macc.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index d65c31b73..fe5b5f662 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -5,6 +5,6 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 38 t:SB_LUT4 -select -assert-count 6 t:SB_CARRY +select -assert-count 3 t:SB_CARRY select -assert-count 7 t:SB_DFFSR select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D