riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

QLF_TDP36K: test bram_tdp post synth

This commit is contained in:
Krystine Sherwin 2023-12-01 09:47:46 +13:00 committed by Martin Povišer
parent f9c8978128
commit ba3be3fd1c
2 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
View File

@ -1,5 +1,8 @@
read_verilog bram_tdp.v
hierarchy -top BRAM_TDP
synth_quicklogic -family qlf_k6n10f
read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
read_verilog -formal bram_tdp.v bram_tdp_tb.v
read_verilog -formal bram_tdp_tb.v
hierarchy -top TB
proc
sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd
sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd

4
tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
View File

@ -63,10 +63,10 @@ wire wce_b = wce_b_testvector[i];
wire [ADDR_WIDTH-1:0] wa_b = wa_b_testvector[i];
wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i];
uut #(
BRAM_TDP #(
.AWIDTH(ADDR_WIDTH),
.DWIDTH(DATA_WIDTH)
) BRAM_TDP (
) uut (
.clk_a(clk),
.rce_a(rce_a),
.ra_a(ra_a),