From ba3be3fd1c0051e8b02b51246fbcff437418b39b Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 1 Dec 2023 09:47:46 +1300
Subject: [PATCH] QLF_TDP36K: test bram_tdp post synth

---
 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys   | 7 +++++--
 tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 4 ++--
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
index 89fcf4472..635769cc0 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
+++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
@@ -1,5 +1,8 @@
+read_verilog bram_tdp.v
+hierarchy -top BRAM_TDP
+synth_quicklogic -family qlf_k6n10f
 read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
-read_verilog -formal bram_tdp.v bram_tdp_tb.v
+read_verilog -formal bram_tdp_tb.v
 hierarchy -top TB
 proc
-sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd
\ No newline at end of file
+sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd
diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
index 0d5d9159d..5d4fbe067 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
+++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
@@ -63,10 +63,10 @@ wire wce_b = wce_b_testvector[i];
 wire [ADDR_WIDTH-1:0] wa_b = wa_b_testvector[i];
 wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i];
 
-uut #(
+BRAM_TDP #(
 	.AWIDTH(ADDR_WIDTH),
 	.DWIDTH(DATA_WIDTH)
-) BRAM_TDP (
+) uut (
 	.clk_a(clk),
 	.rce_a(rce_a),
 	.ra_a(ra_a),