set default_nettype to wire for resetall

2022-08-10 13:28:19 +02:00 · 2022-08-10 13:28:19 +02:00 · b76c72056b
parent 545a3417c8
commit b76c72056b
1 changed files with 1 additions and 0 deletions
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@ -961,6 +961,7 @@ frontend_verilog_preproc(std::istream                 &f,
 		}

 		if (tok == "`resetall") {
+			default_nettype_wire = true;
 			continue;
 		}