From b76c72056b37d8f2b84948cbdc302b149577e648 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 10 Aug 2022 13:28:19 +0200
Subject: [PATCH] set default_nettype to wire for resetall

---
 frontends/verilog/preproc.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 9781a22d9..e33b0a2c3 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -961,6 +961,7 @@ frontend_verilog_preproc(std::istream                 &f,
 		}
 
 		if (tok == "`resetall") {
+			default_nettype_wire = true;
 			continue;
 		}