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set default_nettype to wire for resetall

This commit is contained in:
Miodrag Milanovic 2022-08-10 13:28:19 +02:00
parent 545a3417c8
commit b76c72056b
1 changed files with 1 additions and 0 deletions
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frontends/verilog/preproc.cc
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@ -961,6 +961,7 @@ frontend_verilog_preproc(std::istream &f,
} }
if (tok == "`resetall") { if (tok == "`resetall") {
default_nettype_wire = true;
continue; continue;
} }