riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/master' into ice40dsp

This commit is contained in:
Eddie Hung 2019-07-18 20:37:39 -07:00
parent 15c2a79ab9 9cb0456b6f
commit a777be3091
1 changed files with 18 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
techlibs/intel/synth_intel.cc
View File

@ -38,9 +38,9 @@ struct SynthIntelPass : public ScriptPass {
log("\n"); log("\n");
log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n"); log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n"); log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if not family argument specified.\n"); log(" MAX10 is the default target if no family argument specified.\n");
log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n"); log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n"); log(" Cyclone V and Arria 10 GX devices are experimental.\n");
log("\n"); log("\n");
log(" -top <module>\n"); log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n"); log(" use the specified module as top module (default='top')\n");
@ -62,10 +62,10 @@ struct SynthIntelPass : public ScriptPass {
log(" synonymous to the end of the command list.\n"); log(" synonymous to the end of the command list.\n");
log("\n"); log("\n");
log(" -noiopads\n"); log(" -noiopads\n");
log(" do not use altsyncram cells in output netlist\n"); log(" do not use IO pad cells in output netlist\n");
log("\n"); log("\n");
log(" -nobram\n"); log(" -nobram\n");
log(" do not use altsyncram cells in output netlist\n"); log(" do not use block RAM cells in output netlist\n");
log("\n"); log("\n");
log(" -noflatten\n"); log(" -noflatten\n");
log(" do not flatten design before synthesis\n"); log(" do not flatten design before synthesis\n");
@ -147,9 +147,13 @@ struct SynthIntelPass : public ScriptPass {
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" && if (family_opt != "max10" &&
family_opt != "cycloneive" && family_opt != "cyclone10") family_opt != "a10gx" &&
log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); family_opt != "cyclonev" &&
family_opt != "cycloneiv" &&
family_opt != "cycloneive" &&
family_opt != "cyclone10")
log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
log_header(design, "Executing SYNTH_INTEL pass.\n"); log_header(design, "Executing SYNTH_INTEL pass.\n");
log_push(); log_push();
@ -162,18 +166,9 @@ struct SynthIntelPass : public ScriptPass {
void script() YS_OVERRIDE void script() YS_OVERRIDE
{ {
if (check_label("begin")) { if (check_label("begin")) {
if (check_label("family") && family_opt == "max10") if (check_label("family"))
run("read_verilog -sv -lib +/intel/max10/cells_sim.v"); run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
else if (check_label("family") && family_opt == "a10gx")
run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
else if (check_label("family") && family_opt == "cyclonev")
run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
else if (check_label("family") && family_opt == "cyclone10")
run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
else if (check_label("family") && family_opt == "cycloneiv")
run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
else
run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
// Misc and common cells // Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v"); run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
run("read_verilog -sv -lib +/intel/common/altpll_bb.v"); run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
@ -191,12 +186,12 @@ struct SynthIntelPass : public ScriptPass {
run("synth -run coarse"); run("synth -run coarse");
} }
if (!nobram && check_label("bram", "(skip if -nobram)")) { if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
run("memory_bram -rules +/intel/common/brams.txt"); run("memory_bram -rules +/intel/common/brams.txt");
run("techmap -map +/intel/common/brams_map.v"); run("techmap -map +/intel/common/brams_map.v");
} }
if (check_label("fine")) { if (check_label("map_ffram")) {
run("opt -fast -mux_undef -undriven -fine -full"); run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map"); run("memory_map");
run("opt -undriven -fine"); run("opt -undriven -fine");
@ -222,18 +217,8 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("map_cells")) { if (check_label("map_cells")) {
if (!noiopads) if (!noiopads)
run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
if (family_opt == "max10") run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
run("techmap -map +/intel/max10/cells_map.v");
else if (family_opt == "a10gx")
run("techmap -map +/intel/a10gx/cells_map.v");
else if (family_opt == "cyclonev")
run("techmap -map +/intel/cyclonev/cells_map.v");
else if (family_opt == "cyclone10")
run("techmap -map +/intel/cyclone10/cells_map.v");
else if (family_opt == "cycloneiv")
run("techmap -map +/intel/cycloneiv/cells_map.v");
else
run("techmap -map +/intel/cycloneive/cells_map.v");
run("dffinit -highlow -ff dffeas q power_up"); run("dffinit -highlow -ff dffeas q power_up");
run("clean -purge"); run("clean -purge");
} }