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Merge pull request #4627 from RCoeurjoly/roland/assume_x

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N. Engelhardt 2024-11-06 16:27:30 +01:00 committed by GitHub
parent 2de24dc1c2 5ea2c6e6e5
commit 9068ec5566
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4 changed files with 26 additions and 2 deletions
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5
kernel/fstdata.cc
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@ -258,7 +258,8 @@ void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t sta
std::string FstData::valueOf(fstHandle signal) std::string FstData::valueOf(fstHandle signal)
{ {
if (past_data.find(signal) == past_data.end()) if (past_data.find(signal) == past_data.end()) {
log_error("Signal id %d not found\n", (int)signal); return std::string(handle_to_var[signal].width, 'x');
}
return past_data[signal]; return past_data[signal];
} }

2
tests/sim/assume_x_first_step.ys Normal file
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@ -0,0 +1,2 @@
read_verilog simple_assign.v
sim -r simple_assign.vcd -scope simple_assign

8
tests/sim/simple_assign.v Normal file
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@ -0,0 +1,8 @@
module simple_assign (
input wire in,
output wire out
);
assign out = in;
endmodule

13
tests/sim/simple_assign.vcd Normal file
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@ -0,0 +1,13 @@
$version Yosys $end
$scope module simple_assign $end
$var wire 1 n2 in $end
$var wire 1 n1 out $end
$upscope $end
$enddefinitions $end
#0
#5
b1 n1
b1 n2
#10
b0 n1
b0 n2