From 5ea2c6e6e56075b9d6402cf93d3e12da46707db5 Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Wed, 2 Oct 2024 11:18:19 +0200 Subject: [PATCH] Assume x values for missing signal data in FST Co-authored-by: Miodrag Milanovic Co-authored-by: Roland Coeurjoly --- kernel/fstdata.cc | 5 +++-- tests/sim/assume_x_first_step.ys | 2 ++ tests/sim/simple_assign.v | 8 ++++++++ tests/sim/simple_assign.vcd | 13 +++++++++++++ 4 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 tests/sim/assume_x_first_step.ys create mode 100644 tests/sim/simple_assign.v create mode 100644 tests/sim/simple_assign.vcd diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc index 65ae3426c..309131e01 100644 --- a/kernel/fstdata.cc +++ b/kernel/fstdata.cc @@ -258,7 +258,8 @@ void FstData::reconstructAllAtTimes(std::vector &signal, uint64_t sta std::string FstData::valueOf(fstHandle signal) { - if (past_data.find(signal) == past_data.end()) - log_error("Signal id %d not found\n", (int)signal); + if (past_data.find(signal) == past_data.end()) { + return std::string(handle_to_var[signal].width, 'x'); + } return past_data[signal]; } diff --git a/tests/sim/assume_x_first_step.ys b/tests/sim/assume_x_first_step.ys new file mode 100644 index 000000000..3922e06f6 --- /dev/null +++ b/tests/sim/assume_x_first_step.ys @@ -0,0 +1,2 @@ +read_verilog simple_assign.v +sim -r simple_assign.vcd -scope simple_assign \ No newline at end of file diff --git a/tests/sim/simple_assign.v b/tests/sim/simple_assign.v new file mode 100644 index 000000000..85f3a8bf5 --- /dev/null +++ b/tests/sim/simple_assign.v @@ -0,0 +1,8 @@ +module simple_assign ( + input wire in, + output wire out +); + + assign out = in; + +endmodule diff --git a/tests/sim/simple_assign.vcd b/tests/sim/simple_assign.vcd new file mode 100644 index 000000000..c4494fadf --- /dev/null +++ b/tests/sim/simple_assign.vcd @@ -0,0 +1,13 @@ +$version Yosys $end +$scope module simple_assign $end +$var wire 1 n2 in $end +$var wire 1 n1 out $end +$upscope $end +$enddefinitions $end +#0 +#5 +b1 n1 +b1 n2 +#10 +b0 n1 +b0 n2 \ No newline at end of file