mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3269 from YosysHQ/micko/fix_autotop
Reorder steps in -auto-top to fix synth command, fixes #3261
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8a1d531b25
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@ -976,6 +976,19 @@ struct HierarchyPass : public Pass {
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if (mod->get_bool_attribute(ID::top))
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top_mod = mod;
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if (top_mod == nullptr && auto_top_mode) {
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log_header(design, "Finding top of design hierarchy..\n");
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dict<Module*, int> db;
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for (Module *mod : design->selected_modules()) {
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int score = find_top_mod_score(design, mod, db);
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log("root of %3d design levels: %-20s\n", score, log_id(mod));
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if (!top_mod || score > db[top_mod])
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top_mod = mod;
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}
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if (top_mod != nullptr)
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log("Automatically selected %s as design top module.\n", log_id(top_mod));
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}
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if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
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IdString top_name = top_mod->name.substr(strlen("$abstract"));
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@ -1000,19 +1013,6 @@ struct HierarchyPass : public Pass {
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}
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}
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if (top_mod == nullptr && auto_top_mode) {
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log_header(design, "Finding top of design hierarchy..\n");
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dict<Module*, int> db;
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for (Module *mod : design->selected_modules()) {
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int score = find_top_mod_score(design, mod, db);
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log("root of %3d design levels: %-20s\n", score, log_id(mod));
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if (!top_mod || score > db[top_mod])
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top_mod = mod;
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}
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if (top_mod != nullptr)
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log("Automatically selected %s as design top module.\n", log_id(top_mod));
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}
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if (flag_simcheck && top_mod == nullptr)
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log_error("Design has no top module.\n");
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