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Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp

This commit is contained in:
Eddie Hung 2019-07-19 13:18:20 -07:00
parent bba72f03dd bcd8027182
commit 8791e0caac
2 changed files with 121 additions and 3 deletions
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29
passes/opt/wreduce.cc
View File

@ -342,9 +342,9 @@ struct WreduceWorker
}
}
if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor"))
if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor", "$sub"))
{
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
bool is_signed = cell->getParam("\\A_SIGNED").as_bool() || cell->type == "$sub";
int a_size = 0, b_size = 0;
if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A"));
@ -352,7 +352,7 @@ struct WreduceWorker
int max_y_size = max(a_size, b_size);
if (cell->type == "$add")
if (cell->type.in("$add", "$sub"))
max_y_size++;
if (cell->type == "$mul")
@ -365,6 +365,29 @@ struct WreduceWorker
}
}
if (cell->type.in("$add", "$sub")) {
SigSpec A = cell->getPort("\\A");
SigSpec B = cell->getPort("\\B");
bool sub = cell->type == "$sub";
int i;
for (i = 0; i < GetSize(sig); i++) {
if (B[i] != S0 && (sub || A[i] != S0))
break;
if (B[i] == S0)
module->connect(sig[i], A[i]);
else if (A[i] == S0)
module->connect(sig[i], B[i]);
else log_abort();
}
if (i > 0) {
cell->setPort("\\A", A.extract(i, -1));
cell->setPort("\\B", B.extract(i, -1));
sig.remove(0, i);
bits_removed += i;
}
}
if (GetSize(sig) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
module->remove(cell);

95
tests/various/wreduce.ys Normal file
View File

@ -0,0 +1,95 @@
read_verilog <<EOT
module wreduce_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (i << 4) + j;
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
prep # calls wreduce
select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
##########
read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = j - (i << 4);
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
prep # calls wreduce
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
##########
read_verilog <<EOT
module wreduce_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (i << 4) - j;
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
prep # calls wreduce
select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
##########
read_verilog <<EOT
module wreduce_sub_test3(input [3:0] i, input [7:0] j, output [8:0] o);
assign o = (j >> 4) - i;
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
prep # calls wreduce
dump
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter