From 25ff27e37fcb12c6a298267eda2464431304d713 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 12:34:04 -0700 Subject: [PATCH 1/7] SigSpec::extract to take negative lengths --- kernel/rtlil.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a09f4a0d1..85b013bdc 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3353,7 +3353,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector(bits_.begin() + offset, bits_.begin() + offset + length); + return std::vector(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) From 3839bd50f28a16f1253a56d5871465763e72180c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 12:43:02 -0700 Subject: [PATCH 2/7] Add test --- tests/various/wreduce.ys | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 tests/various/wreduce.ys diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys new file mode 100644 index 000000000..0b5403fa1 --- /dev/null +++ b/tests/various/wreduce.ys @@ -0,0 +1,22 @@ + +read_verilog < Date: Fri, 19 Jul 2019 12:50:11 -0700 Subject: [PATCH 3/7] Add tests for sub too --- tests/various/wreduce.ys | 49 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index 0b5403fa1..ee03e008d 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -5,7 +5,7 @@ module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o); endmodule EOT -hierarchy -top wreduce_add_test +hierarchy -auto-top proc design -save gold @@ -20,3 +20,50 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + + +### X - 0 +read_verilog < Date: Fri, 19 Jul 2019 12:50:21 -0700 Subject: [PATCH 4/7] wreduce for $sub --- passes/opt/wreduce.cc | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 1fbc41082..e8c2cb726 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -365,6 +365,29 @@ struct WreduceWorker } } + if (cell->type.in("$add", "$sub")) { + SigSpec A = cell->getPort("\\A"); + SigSpec B = cell->getPort("\\B"); + bool sub = cell->type == "$sub"; + + int i; + for (i = 0; i < GetSize(sig); i++) { + if (B[i] != S0 && (sub || A[i] != S0)) + break; + if (B[i] == S0) + module->connect(sig[i], A[i]); + else if (A[i] == S0) + module->connect(sig[i], B[i]); + else log_abort(); + } + if (i > 0) { + cell->setPort("\\A", A.extract(i, -1)); + cell->setPort("\\B", B.extract(i, -1)); + sig.remove(0, i); + bits_removed += i; + } + } + if (GetSize(sig) == 0) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); module->remove(cell); From 415a2716df8c41193650804158281ef73e7fc655 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 12:53:18 -0700 Subject: [PATCH 5/7] Be more explicit --- tests/various/wreduce.ys | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index ee03e008d..f9e5ed4e3 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -1,6 +1,6 @@ read_verilog < Date: Fri, 19 Jul 2019 13:11:30 -0700 Subject: [PATCH 6/7] Add one more test with trimming Y_WIDTH of $sub --- tests/various/wreduce.ys | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index f9e5ed4e3..8030c005e 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -9,7 +9,7 @@ hierarchy -auto-top proc design -save gold -prep +prep # calls wreduce select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i @@ -21,8 +21,8 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +########## -### X - 0 read_verilog <> 4) - i; endmodule EOT @@ -79,9 +81,10 @@ hierarchy -auto-top proc design -save gold -prep +prep # calls wreduce -select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i +dump +select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i design -stash gate From bcd802718256efbacaf0a73f99347af40b61e464 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 13:11:48 -0700 Subject: [PATCH 7/7] Also optimise MSB of $sub --- passes/opt/wreduce.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index e8c2cb726..dff1c5370 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -342,9 +342,9 @@ struct WreduceWorker } } - if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor")) + if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor", "$sub")) { - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + bool is_signed = cell->getParam("\\A_SIGNED").as_bool() || cell->type == "$sub"; int a_size = 0, b_size = 0; if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A")); @@ -352,7 +352,7 @@ struct WreduceWorker int max_y_size = max(a_size, b_size); - if (cell->type == "$add") + if (cell->type.in("$add", "$sub")) max_y_size++; if (cell->type == "$mul")