riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #2192 from YosysHQ/verific_netbus_attr 

verific - import attributes for net buses
This commit is contained in:
clairexen 2020-06-25 16:40:30 +02:00 committed by GitHub
parent 0835a86e30 4aec50a863
commit 7d795d6fc7
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
frontends/verific/verific.cc
View File

@ -1109,7 +1109,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size()); RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex()); wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
import_attributes(wire->attributes, netbus, nl); MapIter mibus;
FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
import_attributes(wire->attributes, net, nl);
break;
}
RTLIL::Const initval = Const(State::Sx, GetSize(wire)); RTLIL::Const initval = Const(State::Sx, GetSize(wire));
bool initval_valid = false; bool initval_valid = false;