diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1630c57bc..6637c214d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1109,7 +1109,11 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 			RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
 			wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
-			import_attributes(wire->attributes, netbus, nl);
+			MapIter mibus;
+			FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
+				import_attributes(wire->attributes, net, nl);
+				break;
+			}
 
 			RTLIL::Const initval = Const(State::Sx, GetSize(wire));
 			bool initval_valid = false;