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Add missing u sram init (#3) 

add missing INIT for uSRAM
This commit is contained in:
Tony Min 2024-07-04 16:39:10 -04:00 committed by GitHub
parent e9ff5f7d91
commit 6fe0e00050
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GPG Key ID: B5690EEEBB952194
4 changed files with 64 additions and 14 deletions
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21
techlibs/microchip/brams_defs.vh
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@ -38,6 +38,20 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
.INIT18(slice_init_LSRAM(18)), \ .INIT18(slice_init_LSRAM(18)), \
.INIT19(slice_init_LSRAM(19)) .INIT19(slice_init_LSRAM(19))
`define PARAMS_INIT_uSRAM \
.INIT0(slice_init_uSRAM(00)), \
.INIT1(slice_init_uSRAM(01)), \
.INIT2(slice_init_uSRAM(02)), \
.INIT3(slice_init_uSRAM(03)), \
.INIT4(slice_init_uSRAM(04)), \
.INIT5(slice_init_uSRAM(05)), \
.INIT6(slice_init_uSRAM(06)), \
.INIT7(slice_init_uSRAM(07)), \
.INIT8(slice_init_uSRAM(08)), \
.INIT9(slice_init_uSRAM(09)), \
.INIT10(slice_init_uSRAM(10)), \
.INIT11(slice_init_uSRAM(11)) \
// Helper function for initializing the LSRAM // Helper function for initializing the LSRAM
function [1023:0] slice_init_LSRAM; function [1023:0] slice_init_LSRAM;
input integer slice_idx; input integer slice_idx;
@ -46,3 +60,10 @@ function [1023:0] slice_init_LSRAM;
slice_init_LSRAM[i] = INIT[(slice_idx * 1024 + i)]; slice_init_LSRAM[i] = INIT[(slice_idx * 1024 + i)];
endfunction endfunction
// Helper function for initializing the uSRAM
function [63:0] slice_init_uSRAM;
input integer slice_idx;
integer i;
for (i = 0; i < 64; i = i + 1)
slice_init_uSRAM[i] = INIT[(slice_idx * 64 + i)];
endfunction

13
techlibs/microchip/cells_sim.v
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@ -847,4 +847,17 @@ module RAM64x12 (
input BUSY_FB, input BUSY_FB,
output ACCESS_BUSY output ACCESS_BUSY
); );
parameter INIT0 = 64'h0;
parameter INIT1 = 64'h0;
parameter INIT2 = 64'h0;
parameter INIT3 = 64'h0;
parameter INIT4 = 64'h0;
parameter INIT5 = 64'h0;
parameter INIT6 = 64'h0;
parameter INIT7 = 64'h0;
parameter INIT8 = 64'h0;
parameter INIT9 = 64'h0;
parameter INIT10 = 64'h0;
parameter INIT11 = 64'h0;
endmodule endmodule

12
techlibs/microchip/uSRAM_map.v
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@ -38,7 +38,11 @@ input PORT_W_WR_EN;
input [ADDR_BITS-1:0] PORT_R_ADDR; input [ADDR_BITS-1:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
RAM64x12 _TECHMAP_REPLACE_ ( `include "brams_defs.vh"
RAM64x12 #(
`PARAMS_INIT_uSRAM
) _TECHMAP_REPLACE_ (
.R_ADDR(PORT_R_ADDR), .R_ADDR(PORT_R_ADDR),
.R_ADDR_BYPASS(1'b1), .R_ADDR_BYPASS(1'b1),
.R_ADDR_EN(1'b0), .R_ADDR_EN(1'b0),
@ -88,7 +92,11 @@ input PORT_R_RD_EN;
input [ADDR_BITS-1:0] PORT_R_ADDR; input [ADDR_BITS-1:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
RAM64x12 _TECHMAP_REPLACE_ ( `include "brams_defs.vh"
RAM64x12 #(
`PARAMS_INIT_uSRAM
) _TECHMAP_REPLACE_ (
.R_CLK(PORT_R_CLK), .R_CLK(PORT_R_CLK),
.R_ADDR(PORT_R_ADDR), .R_ADDR(PORT_R_ADDR),
.R_ADDR_BYPASS(1'b0), .R_ADDR_BYPASS(1'b0),

32
tests/arch/microchip/uram_sr.v
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@ -17,16 +17,24 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/ */
module uram_sr(clk, wr, raddr, din, waddr, dout); module uram_sr(clk, wr, raddr, din, waddr, dout);
input clk; input clk;
input [11:0] din; input [11:0] din;
input wr; input wr;
input [5:0] waddr, raddr; input [5:0] waddr, raddr;
output [11:0] dout; output [11:0] dout;
reg [5:0] raddr_reg; reg [5:0] raddr_reg;
reg [11:0] mem [0:63]; reg [11:0] mem [0:63];
assign dout = mem[raddr_reg]; assign dout = mem[raddr_reg];
always@(posedge clk) begin
raddr_reg <= raddr; if(wr) integer i;
mem[waddr]<= din; initial begin
end for (i = 0; i < 64; i = i + 1) begin
mem[i] = 12'hfff;
end
end
always@(posedge clk) begin
raddr_reg <= raddr; if(wr)
mem[waddr]<= din;
end
endmodule endmodule