From 6fe0e00050506db886f32af31539ffd8c09a5ab6 Mon Sep 17 00:00:00 2001
From: Tony Min <170435972+tony-min-1@users.noreply.github.com>
Date: Thu, 4 Jul 2024 16:39:10 -0400
Subject: [PATCH] Add missing u sram init (#3)

add missing INIT for uSRAM
---
 techlibs/microchip/brams_defs.vh | 21 +++++++++++++++++++++
 techlibs/microchip/cells_sim.v   | 13 +++++++++++++
 techlibs/microchip/uSRAM_map.v   | 12 ++++++++++--
 tests/arch/microchip/uram_sr.v   | 32 ++++++++++++++++++++------------
 4 files changed, 64 insertions(+), 14 deletions(-)

diff --git a/techlibs/microchip/brams_defs.vh b/techlibs/microchip/brams_defs.vh
index 157945fdb..e02d2a83d 100644
--- a/techlibs/microchip/brams_defs.vh
+++ b/techlibs/microchip/brams_defs.vh
@@ -38,6 +38,20 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 	.INIT18(slice_init_LSRAM(18)), \
 	.INIT19(slice_init_LSRAM(19))
 
+`define PARAMS_INIT_uSRAM \
+	.INIT0(slice_init_uSRAM(00)), \
+	.INIT1(slice_init_uSRAM(01)), \
+	.INIT2(slice_init_uSRAM(02)), \
+	.INIT3(slice_init_uSRAM(03)), \
+	.INIT4(slice_init_uSRAM(04)), \
+	.INIT5(slice_init_uSRAM(05)), \
+	.INIT6(slice_init_uSRAM(06)), \
+	.INIT7(slice_init_uSRAM(07)), \
+	.INIT8(slice_init_uSRAM(08)), \
+	.INIT9(slice_init_uSRAM(09)), \
+	.INIT10(slice_init_uSRAM(10)), \
+	.INIT11(slice_init_uSRAM(11)) \
+
 // Helper function for initializing the LSRAM
 function [1023:0] slice_init_LSRAM;
 	input integer slice_idx;
@@ -46,3 +60,10 @@ function [1023:0] slice_init_LSRAM;
 		slice_init_LSRAM[i] = INIT[(slice_idx * 1024 + i)];
 endfunction
 
+// Helper function for initializing the uSRAM
+function [63:0] slice_init_uSRAM;
+	input integer slice_idx;
+	integer i;
+	for (i = 0; i < 64; i = i + 1)
+		slice_init_uSRAM[i] = INIT[(slice_idx * 64 + i)];
+endfunction
\ No newline at end of file
diff --git a/techlibs/microchip/cells_sim.v b/techlibs/microchip/cells_sim.v
index f3b55fe4c..eb06a0e69 100644
--- a/techlibs/microchip/cells_sim.v
+++ b/techlibs/microchip/cells_sim.v
@@ -847,4 +847,17 @@ module RAM64x12 (
 	input		BUSY_FB,
 	output		ACCESS_BUSY
 );
+parameter INIT0 = 64'h0;
+parameter INIT1 = 64'h0;
+parameter INIT2 = 64'h0;
+parameter INIT3 = 64'h0;
+parameter INIT4 = 64'h0;
+parameter INIT5 = 64'h0;
+parameter INIT6 = 64'h0;
+parameter INIT7 = 64'h0;
+parameter INIT8 = 64'h0;
+parameter INIT9 = 64'h0;
+parameter INIT10 = 64'h0;
+parameter INIT11 = 64'h0;
+
 endmodule
\ No newline at end of file
diff --git a/techlibs/microchip/uSRAM_map.v b/techlibs/microchip/uSRAM_map.v
index 242b027a9..5750a780f 100644
--- a/techlibs/microchip/uSRAM_map.v
+++ b/techlibs/microchip/uSRAM_map.v
@@ -38,7 +38,11 @@ input PORT_W_WR_EN;
 input [ADDR_BITS-1:0] PORT_R_ADDR;
 output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
 
-RAM64x12 _TECHMAP_REPLACE_ (
+`include "brams_defs.vh"
+
+RAM64x12 #(
+	`PARAMS_INIT_uSRAM
+) _TECHMAP_REPLACE_ (
 	.R_ADDR(PORT_R_ADDR),
 	.R_ADDR_BYPASS(1'b1),
 	.R_ADDR_EN(1'b0),
@@ -88,7 +92,11 @@ input PORT_R_RD_EN;
 input [ADDR_BITS-1:0] PORT_R_ADDR;
 output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
 
-RAM64x12 _TECHMAP_REPLACE_ (
+`include "brams_defs.vh"
+
+RAM64x12 #(
+	`PARAMS_INIT_uSRAM
+) _TECHMAP_REPLACE_ (
 	.R_CLK(PORT_R_CLK),
 	.R_ADDR(PORT_R_ADDR),
 	.R_ADDR_BYPASS(1'b0),
diff --git a/tests/arch/microchip/uram_sr.v b/tests/arch/microchip/uram_sr.v
index 1852dfc68..7bab189fe 100644
--- a/tests/arch/microchip/uram_sr.v
+++ b/tests/arch/microchip/uram_sr.v
@@ -17,16 +17,24 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module uram_sr(clk, wr, raddr, din, waddr, dout);
-input clk;
-input [11:0] din;
-input wr;
-input [5:0] waddr, raddr;
-output [11:0] dout;
-reg [5:0] raddr_reg;
-reg [11:0] mem [0:63];
-assign dout = mem[raddr_reg];
-always@(posedge clk) begin
-	raddr_reg <= raddr; if(wr)
-	mem[waddr]<= din;
-end
+	input clk;
+	input [11:0] din;
+	input wr;
+	input [5:0] waddr, raddr;
+	output [11:0] dout;
+	reg [5:0] raddr_reg;
+	reg [11:0] mem [0:63];
+	assign dout = mem[raddr_reg];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 64; i = i + 1) begin
+			mem[i] = 12'hfff;
+		end
+	end
+
+	always@(posedge clk) begin
+		raddr_reg <= raddr; if(wr)
+		mem[waddr]<= din;
+	end
 endmodule
\ No newline at end of file