mirror of https://github.com/YosysHQ/yosys.git
863 lines
14 KiB
Verilog
863 lines
14 KiB
Verilog
/*
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ISC License
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Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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Permission to use, copy, modify, and/or distribute this software for any
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purpose with or without fee is hereby granted, provided that the above
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copyright notice and this permission notice appear in all copies.
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THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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// Macro Library for PolarFire https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
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module AND2 (
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input A, B,
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output Y
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);
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assign Y = A & B;
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endmodule
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module AND3 (
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input A, B, C,
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output Y
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);
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assign Y = A & B & C;
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endmodule
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module AND4 (
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input A, B, C, D,
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output Y
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);
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assign Y = A & B & C & D;
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endmodule
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(* abc9_lut=1 *)
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module CFG1 (
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output Y,
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input A
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);
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parameter [1:0] INIT = 2'h0;
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assign Y = INIT >> A;
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specify
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(A => Y) = 127;
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endspecify
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endmodule
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(* abc9_lut=2 *)
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module CFG2 (
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output Y,
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input A,
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input B
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);
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parameter [3:0] INIT = 4'h0;
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assign Y = INIT >> {B, A};
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specify
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(A => Y) = 238;
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(B => Y) = 127;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module CFG3 (
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output Y,
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input A,
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input B,
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input C
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);
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parameter [7:0] INIT = 8'h0;
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assign Y = INIT >> {C, B, A};
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specify
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(A => Y) = 407;
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(B => Y) = 238;
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(C => Y) = 127;
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endspecify
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endmodule
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(* abc9_lut=3 *)
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module CFG4 (
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output Y,
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input A,
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input B,
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input C,
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input D
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);
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parameter [15:0] INIT = 16'h0;
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assign Y = INIT >> {D, C, B, A};
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specify
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(A => Y) = 472;
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(B => Y) = 407;
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(C => Y) = 238;
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(D => Y) = 127;
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endspecify
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endmodule
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module BUFF (
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input A,
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output Y
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);
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assign Y = A;
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endmodule
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module BUFD (
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input A,
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output Y
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);
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assign Y = A;
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endmodule
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module CLKINT (
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input A,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A;
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endmodule
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module CLKINT_PRESERVE (
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input A,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A;
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endmodule
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module GCLKINT (
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input A, EN,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A & EN;
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endmodule
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module RCLKINT (
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input A,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A;
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endmodule
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module RGCLKINT (
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input A, EN,
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(* clkbuf_driver *)
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output Y
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);
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assign Y = A & EN;
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endmodule
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// sequential elements
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// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
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// see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html
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(* abc9_flop, lib_whitebox *)
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module MICROCHIP_SYNC_SET_DFF(
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input D,
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input CLK,
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input Set,
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input En,
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output reg Q);
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parameter [0:0] INIT = 1'b0; // unused
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always @(posedge CLK) begin
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if (En == 1) begin
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if (Set == 0)
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Q <= 1;
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else
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Q <= D;
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end
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end
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specify
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$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
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$setup(En, posedge CLK, 109);
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$setup(Set, posedge CLK &&& En, 404);
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if (En && !Set) (posedge CLK => (Q : 1'b1)) = 303;
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if (En && Set) (posedge CLK => (Q : D)) = 303;
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endspecify
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endmodule
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(* abc9_flop, lib_whitebox *)
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module MICROCHIP_SYNC_RESET_DFF(
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input D,
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input CLK,
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input Reset,
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input En,
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output reg Q);
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parameter [0:0] INIT = 1'b0; // unused
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always @(posedge CLK) begin
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if (En == 1) begin
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if (Reset == 0)
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Q <= 0;
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else
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Q <= D;
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end
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end
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specify
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$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
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$setup(En, posedge CLK, 109);
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$setup(Reset, posedge CLK &&& En, 404);
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if (En && !Reset) (posedge CLK => (Q : 1'b0)) = 303;
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if (En && Reset) (posedge CLK => (Q : D)) = 303;
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endspecify
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endmodule
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module SLE (
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output Q,
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input ADn,
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input ALn,
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(* clkbuf_sink *)
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input CLK,
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input D,
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input LAT,
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input SD,
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input EN,
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input SLn
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);
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reg q_latch, q_ff;
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always @(posedge CLK, negedge ALn) begin
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if (!ALn) begin
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q_ff <= !ADn;
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end else if (EN) begin
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if (!SLn)
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q_ff <= SD;
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else
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q_ff <= D;
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end
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end
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always @* begin
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if (!ALn) begin
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q_latch <= !ADn;
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end else if (CLK && EN) begin
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if (!SLn)
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q_ff <= SD;
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else
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q_ff <= D;
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end
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end
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assign Q = LAT ? q_latch : q_ff;
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endmodule
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(* abc9_box, lib_whitebox *)
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module ARI1 (
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(* abc9_carry *)
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input FCI,
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(* abc9_carry *)
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output FCO,
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input A, B, C, D,
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output Y, S
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);
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parameter [19:0] INIT = 20'h0;
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wire [2:0] Fsel = {D, C, B};
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wire F0 = INIT[Fsel];
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wire F1 = INIT[8 + Fsel];
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wire Yout = A ? F1 : F0;
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assign Y = Yout;
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assign S = FCI ^ Yout;
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wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
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wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
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assign FCO = P ? FCI : G;
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specify
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//pin to pin path delay
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(A => Y ) = 472;
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(B => Y ) = 407;
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(C => Y ) = 238;
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(D => Y ) = 127;
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(A => S ) = 572;
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(B => S ) = 507;
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(C => S ) = 338;
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(D => S ) = 227;
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(FCI => S ) = 100;
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(A => FCO ) = 522;
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(B => FCO ) = 457;
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(C => FCO ) = 288;
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(D => FCO ) = 177;
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(FCI => FCO ) = 50;
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endspecify
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endmodule
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// module FCEND_BUFF
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// module FCINIT_BUFF
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// module FLASH_FREEZE
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// module OSCILLATOR
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// module SYSCTRL_RESET_STATUS
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// module LIVE_PROBE_FB
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(* blackbox *)
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module GCLKBUF (
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(* iopad_external_pin *)
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input PAD,
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input EN,
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(* clkbuf_driver *)
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output Y
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);
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endmodule
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(* blackbox *)
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module GCLKBUF_DIFF (
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(* iopad_external_pin *)
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input PADP,
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(* iopad_external_pin *)
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input PADN,
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input EN,
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(* clkbuf_driver *)
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output Y
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);
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endmodule
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(* blackbox *)
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module GCLKBIBUF (
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input D,
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input E,
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input EN,
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(* iopad_external_pin *)
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inout PAD,
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(* clkbuf_driver *)
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output Y
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);
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endmodule
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// module DFN1
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// module DFN1C0
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// module DFN1E1
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// module DFN1E1C0
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// module DFN1E1P0
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// module DFN1P0
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// module DLN1
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// module DLN1C0
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// module DLN1P0
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module INV (
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input A,
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output Y
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);
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assign Y = !A;
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endmodule
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module INVD (
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input A,
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output Y
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);
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assign Y = !A;
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endmodule
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module MX2 (
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input A, B, S,
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output Y
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);
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assign Y = S ? B : A;
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endmodule
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module MX4 (
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input D0, D1, D2, D3, S0, S1,
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output Y
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);
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assign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);
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endmodule
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module NAND2 (
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input A, B,
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output Y
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);
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assign Y = !(A & B);
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endmodule
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module NAND3 (
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input A, B, C,
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output Y
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);
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assign Y = !(A & B & C);
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endmodule
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module NAND4 (
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input A, B, C, D,
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output Y
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);
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assign Y = !(A & B & C & D);
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endmodule
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module NOR2 (
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input A, B,
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output Y
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);
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assign Y = !(A | B);
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endmodule
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module NOR3 (
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input A, B, C,
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output Y
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);
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assign Y = !(A | B | C);
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endmodule
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module NOR4 (
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input A, B, C, D,
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output Y
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);
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assign Y = !(A | B | C | D);
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endmodule
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module OR2 (
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input A, B,
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output Y
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);
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assign Y = A | B;
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endmodule
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module OR3 (
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input A, B, C,
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output Y
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);
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assign Y = A | B | C;
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endmodule
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module OR4 (
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input A, B, C, D,
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output Y
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);
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assign Y = A | B | C | D;
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endmodule
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module XOR2 (
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input A, B,
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output Y
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);
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assign Y = A ^ B;
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endmodule
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module XOR3 (
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input A, B, C,
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output Y
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);
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assign Y = A ^ B ^ C;
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endmodule
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module XOR4 (
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input A, B, C, D,
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output Y
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);
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assign Y = A ^ B ^ C ^ D;
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endmodule
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module XOR8 (
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input A, B, C, D, E, F, G, H,
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output Y
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);
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assign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;
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endmodule
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// module UJTAG
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module BIBUF (
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input D,
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input E,
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(* iopad_external_pin *)
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inout PAD,
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output Y
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);
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parameter IOSTD = "";
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assign PAD = E ? D : 1'bz;
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assign Y = PAD;
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endmodule
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(* blackbox *)
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module BIBUF_DIFF (
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input D,
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input E,
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(* iopad_external_pin *)
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inout PADP,
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(* iopad_external_pin *)
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inout PADN,
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output Y
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);
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parameter IOSTD = "";
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endmodule
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module CLKBIBUF (
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input D,
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input E,
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(* iopad_external_pin *)
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inout PAD,
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(* clkbuf_driver *)
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output Y
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);
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parameter IOSTD = "";
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assign PAD = E ? D : 1'bz;
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assign Y = PAD;
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endmodule
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module CLKBUF (
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(* iopad_external_pin *)
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input PAD,
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(* clkbuf_driver *)
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output Y
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);
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parameter IOSTD = "";
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assign Y = PAD;
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specify
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(PAD => Y) = 50;
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endspecify
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endmodule
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(* blackbox *)
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module CLKBUF_DIFF (
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(* iopad_external_pin *)
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input PADP,
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(* iopad_external_pin *)
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input PADN,
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(* clkbuf_driver *)
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output Y
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);
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parameter IOSTD = "";
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endmodule
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module INBUF (
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(* iopad_external_pin *)
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input PAD,
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output Y
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);
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parameter IOSTD = "";
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assign Y = PAD;
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endmodule
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(* blackbox *)
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module INBUF_DIFF (
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(* iopad_external_pin *)
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input PADP,
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(* iopad_external_pin *)
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input PADN,
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output Y
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);
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parameter IOSTD = "";
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endmodule
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|
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module OUTBUF (
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input D,
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(* iopad_external_pin *)
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output PAD
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);
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parameter IOSTD = "";
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assign PAD = D;
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endmodule
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|
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(* blackbox *)
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module OUTBUF_DIFF (
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input D,
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(* iopad_external_pin *)
|
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output PADP,
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(* iopad_external_pin *)
|
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output PADN
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);
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parameter IOSTD = "";
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endmodule
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|
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module TRIBUFF (
|
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input D,
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input E,
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(* iopad_external_pin *)
|
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output PAD
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);
|
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parameter IOSTD = "";
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assign PAD = E ? D : 1'bz;
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endmodule
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|
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(* blackbox *)
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module TRIBUFF_DIFF (
|
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input D,
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input E,
|
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(* iopad_external_pin *)
|
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output PADP,
|
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(* iopad_external_pin *)
|
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output PADN
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);
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parameter IOSTD = "";
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endmodule
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|
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// module DDR_IN
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// module DDR_OUT
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// module RAM1K18
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// module RAM64x18
|
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// module MACC
|
|
|
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(* blackbox *)
|
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module SYSRESET (
|
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(* iopad_external_pin *)
|
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input DEVRST_N,
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output POWER_ON_RESET_N);
|
|
endmodule
|
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|
|
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|
(* blackbox *)
|
|
module XTLOSC (
|
|
(* iopad_external_pin *)
|
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input XTL,
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output CLKOUT);
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parameter [1:0] MODE = 2'h3;
|
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parameter real FREQUENCY = 20.0;
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|
endmodule
|
|
|
|
(* blackbox *)
|
|
module RAM1K18 (
|
|
input [13:0] A_ADDR,
|
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input [2:0] A_BLK,
|
|
(* clkbuf_sink *)
|
|
input A_CLK,
|
|
input [17:0] A_DIN,
|
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output [17:0] A_DOUT,
|
|
input [1:0] A_WEN,
|
|
input [2:0] A_WIDTH,
|
|
input A_WMODE,
|
|
input A_ARST_N,
|
|
input A_DOUT_LAT,
|
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input A_DOUT_ARST_N,
|
|
(* clkbuf_sink *)
|
|
input A_DOUT_CLK,
|
|
input A_DOUT_EN,
|
|
input A_DOUT_SRST_N,
|
|
|
|
input [13:0] B_ADDR,
|
|
input [2:0] B_BLK,
|
|
(* clkbuf_sink *)
|
|
input B_CLK,
|
|
input [17:0] B_DIN,
|
|
output [17:0] B_DOUT,
|
|
input [1:0] B_WEN,
|
|
input [2:0] B_WIDTH,
|
|
input B_WMODE,
|
|
input B_ARST_N,
|
|
input B_DOUT_LAT,
|
|
input B_DOUT_ARST_N,
|
|
(* clkbuf_sink *)
|
|
input B_DOUT_CLK,
|
|
input B_DOUT_EN,
|
|
input B_DOUT_SRST_N,
|
|
input A_EN,
|
|
input B_EN,
|
|
input SII_LOCK,
|
|
output BUSY);
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module RAM64x18 (
|
|
input [9:0] A_ADDR,
|
|
input [1:0] A_BLK,
|
|
input [2:0] A_WIDTH,
|
|
output [17:0] A_DOUT,
|
|
input A_DOUT_ARST_N,
|
|
(* clkbuf_sink *)
|
|
input A_DOUT_CLK,
|
|
input A_DOUT_EN,
|
|
input A_DOUT_LAT,
|
|
input A_DOUT_SRST_N,
|
|
(* clkbuf_sink *)
|
|
input A_ADDR_CLK,
|
|
input A_ADDR_EN,
|
|
input A_ADDR_LAT,
|
|
input A_ADDR_SRST_N,
|
|
input A_ADDR_ARST_N,
|
|
|
|
input [9:0] B_ADDR,
|
|
input [1:0] B_BLK,
|
|
input [2:0] B_WIDTH,
|
|
output [17:0] B_DOUT,
|
|
input B_DOUT_ARST_N,
|
|
(* clkbuf_sink *)
|
|
input B_DOUT_CLK,
|
|
input B_DOUT_EN,
|
|
input B_DOUT_LAT,
|
|
input B_DOUT_SRST_N,
|
|
(* clkbuf_sink *)
|
|
input B_ADDR_CLK,
|
|
input B_ADDR_EN,
|
|
input B_ADDR_LAT,
|
|
input B_ADDR_SRST_N,
|
|
input B_ADDR_ARST_N,
|
|
|
|
input [9:0] C_ADDR,
|
|
(* clkbuf_sink *)
|
|
input C_CLK,
|
|
input [17:0] C_DIN,
|
|
input C_WEN,
|
|
input [1:0] C_BLK,
|
|
input [2:0] C_WIDTH,
|
|
|
|
input A_EN,
|
|
input B_EN,
|
|
input C_EN,
|
|
input SII_LOCK,
|
|
output BUSY);
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module MACC_PA (
|
|
input DOTP,
|
|
input SIMD,
|
|
input OVFL_CARRYOUT_SEL,
|
|
input CLK,
|
|
input AL_N,
|
|
input [17:0] A,
|
|
input A_BYPASS,
|
|
input A_SRST_N,
|
|
input A_EN,
|
|
input [17:0] B,
|
|
input B_BYPASS,
|
|
input B_SRST_N,
|
|
input B_EN,
|
|
input [17:0] D,
|
|
input D_BYPASS,
|
|
input D_ARST_N,
|
|
input D_SRST_N,
|
|
input D_EN,
|
|
input CARRYIN,
|
|
input [47:0] C,
|
|
input C_BYPASS,
|
|
input C_ARST_N,
|
|
input C_SRST_N,
|
|
input C_EN,
|
|
input [47:0] CDIN,
|
|
output [47:0] P,
|
|
output OVFL_CARRYOUT,
|
|
input P_BYPASS,
|
|
input P_SRST_N,
|
|
input P_EN,
|
|
output [47:0] CDOUT,
|
|
input PASUB,
|
|
input PASUB_BYPASS,
|
|
input PASUB_AD_N,
|
|
input PASUB_SL_N,
|
|
input PASUB_SD_N,
|
|
input PASUB_EN,
|
|
input [1:0] CDIN_FDBK_SEL,
|
|
input CDIN_FDBK_SEL_BYPASS,
|
|
input [1:0] CDIN_FDBK_SEL_AD_N,
|
|
input CDIN_FDBK_SEL_SL_N,
|
|
input [1:0] CDIN_FDBK_SEL_SD_N,
|
|
input CDIN_FDBK_SEL_EN,
|
|
input ARSHFT17,
|
|
input ARSHFT17_BYPASS,
|
|
input ARSHFT17_AD_N,
|
|
input ARSHFT17_SL_N,
|
|
input ARSHFT17_SD_N,
|
|
input ARSHFT17_EN,
|
|
input SUB,
|
|
input SUB_BYPASS,
|
|
input SUB_AD_N,
|
|
input SUB_SL_N,
|
|
input SUB_SD_N,
|
|
input SUB_EN
|
|
);
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module RAM1K20 (
|
|
input [13:0] A_ADDR,
|
|
input [2:0] A_BLK_EN,
|
|
input A_CLK,
|
|
input [19:0] A_DIN,
|
|
output [19:0] A_DOUT,
|
|
input [1:0] A_WEN,
|
|
input A_REN,
|
|
input [2:0] A_WIDTH,
|
|
input [1:0] A_WMODE,
|
|
input A_BYPASS,
|
|
input A_DOUT_EN,
|
|
input A_DOUT_SRST_N,
|
|
input A_DOUT_ARST_N,
|
|
input [13:0] B_ADDR,
|
|
input [2:0] B_BLK_EN,
|
|
input B_CLK,
|
|
input [19:0] B_DIN,
|
|
output [19:0] B_DOUT,
|
|
input [1:0] B_WEN,
|
|
input B_REN,
|
|
input [2:0] B_WIDTH,
|
|
input [1:0] B_WMODE,
|
|
input B_BYPASS,
|
|
input B_DOUT_EN,
|
|
input B_DOUT_SRST_N,
|
|
input B_DOUT_ARST_N,
|
|
input ECC_EN,
|
|
input ECC_BYPASS,
|
|
output SB_CORRECT,
|
|
output DB_DETECT,
|
|
input BUSY_FB,
|
|
output ACCESS_BUSY
|
|
);
|
|
parameter INIT0 = 1024'h0;
|
|
parameter INIT1 = 1024'h0;
|
|
parameter INIT2 = 1024'h0;
|
|
parameter INIT3 = 1024'h0;
|
|
parameter INIT4 = 1024'h0;
|
|
parameter INIT5 = 1024'h0;
|
|
parameter INIT6 = 1024'h0;
|
|
parameter INIT7 = 1024'h0;
|
|
parameter INIT8 = 1024'h0;
|
|
parameter INIT9 = 1024'h0;
|
|
parameter INIT10 = 1024'h0;
|
|
parameter INIT11 = 1024'h0;
|
|
parameter INIT12 = 1024'h0;
|
|
parameter INIT13 = 1024'h0;
|
|
parameter INIT14 = 1024'h0;
|
|
parameter INIT15 = 1024'h0;
|
|
parameter INIT16 = 1024'h0;
|
|
parameter INIT17 = 1024'h0;
|
|
parameter INIT18 = 1024'h0;
|
|
parameter INIT19 = 1024'h0;
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module RAM64x12 (
|
|
input R_CLK,
|
|
input [5:0] R_ADDR,
|
|
input R_ADDR_BYPASS,
|
|
input R_ADDR_EN,
|
|
input R_ADDR_SL_N,
|
|
input R_ADDR_SD,
|
|
input R_ADDR_AL_N,
|
|
input R_ADDR_AD_N,
|
|
input BLK_EN,
|
|
output [11:0] R_DATA,
|
|
input R_DATA_BYPASS,
|
|
input R_DATA_EN,
|
|
input R_DATA_SL_N,
|
|
input R_DATA_SD,
|
|
input R_DATA_AL_N,
|
|
input R_DATA_AD_N,
|
|
|
|
input W_CLK,
|
|
input [5:0] W_ADDR,
|
|
input [11:0]W_DATA,
|
|
input W_EN,
|
|
|
|
input BUSY_FB,
|
|
output ACCESS_BUSY
|
|
);
|
|
parameter INIT0 = 64'h0;
|
|
parameter INIT1 = 64'h0;
|
|
parameter INIT2 = 64'h0;
|
|
parameter INIT3 = 64'h0;
|
|
parameter INIT4 = 64'h0;
|
|
parameter INIT5 = 64'h0;
|
|
parameter INIT6 = 64'h0;
|
|
parameter INIT7 = 64'h0;
|
|
parameter INIT8 = 64'h0;
|
|
parameter INIT9 = 64'h0;
|
|
parameter INIT10 = 64'h0;
|
|
parameter INIT11 = 64'h0;
|
|
|
|
endmodule |