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Merge remote-tracking branch 'origin/master' into xc7srl

This commit is contained in:
Eddie Hung 2019-03-22 13:10:42 -07:00
parent 4cc6b3e942 a440f82586
commit 46753cf89f
7 changed files with 115 additions and 44 deletions
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33
frontends/ast/ast.cc
View File

@ -45,7 +45,7 @@ namespace AST {
// instantiate global variables (private API) // instantiate global variables (private API)
namespace AST_INTERNAL { namespace AST_INTERNAL {
bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit; bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
AstNode *current_ast, *current_ast_mod; AstNode *current_ast, *current_ast_mod;
std::map<std::string, AstNode*> current_scope; std::map<std::string, AstNode*> current_scope;
@ -431,9 +431,12 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
break; break;
case AST_RANGE: case AST_RANGE:
if (range_valid) if (range_valid) {
if (range_swapped)
fprintf(f, "[%d:%d]", range_right, range_left);
else
fprintf(f, "[%d:%d]", range_left, range_right); fprintf(f, "[%d:%d]", range_left, range_right);
else { } else {
for (auto child : children) { for (auto child : children) {
fprintf(f, "%c", first ? '[' : ':'); fprintf(f, "%c", first ? '[' : ':');
child->dumpVlog(f, ""); child->dumpVlog(f, "");
@ -562,7 +565,8 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
case AST_CONCAT: case AST_CONCAT:
fprintf(f, "{"); fprintf(f, "{");
for (auto child : children) { for (int i = GetSize(children)-1; i >= 0; i--) {
auto child = children[i];
if (!first) if (!first)
fprintf(f, ", "); fprintf(f, ", ");
child->dumpVlog(f, ""); child->dumpVlog(f, "");
@ -926,23 +930,28 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
ast_before_simplify = ast->clone(); ast_before_simplify = ast->clone();
if (flag_dump_ast1) { if (flag_dump_ast1) {
log("Dumping Verilog AST before simplification:\n"); log("Dumping AST before simplification:\n");
ast->dumpAst(NULL, " "); ast->dumpAst(NULL, " ");
log("--- END OF AST DUMP ---\n"); log("--- END OF AST DUMP ---\n");
} }
if (flag_dump_vlog1) {
log("Dumping Verilog AST before simplification:\n");
ast->dumpVlog(NULL, " ");
log("--- END OF AST DUMP ---\n");
}
if (!defer) if (!defer)
{ {
while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { } while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
if (flag_dump_ast2) { if (flag_dump_ast2) {
log("Dumping Verilog AST after simplification:\n"); log("Dumping AST after simplification:\n");
ast->dumpAst(NULL, " "); ast->dumpAst(NULL, " ");
log("--- END OF AST DUMP ---\n"); log("--- END OF AST DUMP ---\n");
} }
if (flag_dump_vlog) { if (flag_dump_vlog2) {
log("Dumping Verilog AST (as requested by dump_vlog option):\n"); log("Dumping Verilog AST after simplification:\n");
ast->dumpVlog(NULL, " "); ast->dumpVlog(NULL, " ");
log("--- END OF AST DUMP ---\n"); log("--- END OF AST DUMP ---\n");
} }
@ -1016,14 +1025,15 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
} }
// create AstModule instances for all modules in the AST tree and add them to 'design' // create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
{ {
current_ast = ast; current_ast = ast;
flag_dump_ast1 = dump_ast1; flag_dump_ast1 = dump_ast1;
flag_dump_ast2 = dump_ast2; flag_dump_ast2 = dump_ast2;
flag_no_dump_ptr = no_dump_ptr; flag_no_dump_ptr = no_dump_ptr;
flag_dump_vlog = dump_vlog; flag_dump_vlog1 = dump_vlog1;
flag_dump_vlog2 = dump_vlog2;
flag_dump_rtlil = dump_rtlil; flag_dump_rtlil = dump_rtlil;
flag_nolatches = nolatches; flag_nolatches = nolatches;
flag_nomeminit = nomeminit; flag_nomeminit = nomeminit;
@ -1357,7 +1367,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
current_ast = NULL; current_ast = NULL;
flag_dump_ast1 = false; flag_dump_ast1 = false;
flag_dump_ast2 = false; flag_dump_ast2 = false;
flag_dump_vlog = false; flag_dump_vlog1 = false;
flag_dump_vlog2 = false;
flag_nolatches = nolatches; flag_nolatches = nolatches;
flag_nomeminit = nomeminit; flag_nomeminit = nomeminit;
flag_nomem2reg = nomem2reg; flag_nomem2reg = nomem2reg;

2
frontends/ast/ast.h
View File

@ -282,7 +282,7 @@ namespace AST
}; };
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
// parametric modules are supported directly by the AST library // parametric modules are supported directly by the AST library

11
frontends/ast/simplify.cc
View File

@ -138,9 +138,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
int mem_width, mem_size, addr_bits; int mem_width, mem_size, addr_bits;
node->meminfo(mem_width, mem_size, addr_bits); node->meminfo(mem_width, mem_size, addr_bits);
int data_range_left = node->children[0]->range_left;
int data_range_right = node->children[0]->range_right;
if (node->children[0]->range_swapped)
std::swap(data_range_left, data_range_right);
for (int i = 0; i < mem_size; i++) { for (int i = 0; i < mem_size; i++) {
AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE,
mkconst_int(mem_width-1, true), mkconst_int(0, true))); mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
reg->str = stringf("%s[%d]", node->str.c_str(), i); reg->str = stringf("%s[%d]", node->str.c_str(), i);
reg->is_reg = true; reg->is_reg = true;
reg->is_signed = node->is_signed; reg->is_signed = node->is_signed;
@ -976,6 +982,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
int data_range_left = id2ast->children[0]->range_left; int data_range_left = id2ast->children[0]->range_left;
int data_range_right = id2ast->children[0]->range_right; int data_range_right = id2ast->children[0]->range_right;
if (id2ast->children[0]->range_swapped)
std::swap(data_range_left, data_range_right);
std::stringstream sstr; std::stringstream sstr;
sstr << "$mem2bits$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++); sstr << "$mem2bits$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
std::string wire_id = sstr.str(); std::string wire_id = sstr.str();

29
frontends/verilog/verilog_frontend.cc
View File

@ -81,6 +81,9 @@ struct VerilogFrontend : public Frontend {
log(" -assert-assumes\n"); log(" -assert-assumes\n");
log(" treat all assume() statements like assert() statements\n"); log(" treat all assume() statements like assert() statements\n");
log("\n"); log("\n");
log(" -debug\n");
log(" alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
log("\n");
log(" -dump_ast1\n"); log(" -dump_ast1\n");
log(" dump abstract syntax tree (before simplification)\n"); log(" dump abstract syntax tree (before simplification)\n");
log("\n"); log("\n");
@ -90,7 +93,10 @@ struct VerilogFrontend : public Frontend {
log(" -no_dump_ptr\n"); log(" -no_dump_ptr\n");
log(" do not include hex memory addresses in dump (easier to diff dumps)\n"); log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
log("\n"); log("\n");
log(" -dump_vlog\n"); log(" -dump_vlog1\n");
log(" dump ast as Verilog code (before simplification)\n");
log("\n");
log(" -dump_vlog2\n");
log(" dump ast as Verilog code (after simplification)\n"); log(" dump ast as Verilog code (after simplification)\n");
log("\n"); log("\n");
log(" -dump_rtlil\n"); log(" -dump_rtlil\n");
@ -197,7 +203,8 @@ struct VerilogFrontend : public Frontend {
bool flag_dump_ast1 = false; bool flag_dump_ast1 = false;
bool flag_dump_ast2 = false; bool flag_dump_ast2 = false;
bool flag_no_dump_ptr = false; bool flag_no_dump_ptr = false;
bool flag_dump_vlog = false; bool flag_dump_vlog1 = false;
bool flag_dump_vlog2 = false;
bool flag_dump_rtlil = false; bool flag_dump_rtlil = false;
bool flag_nolatches = false; bool flag_nolatches = false;
bool flag_nomeminit = false; bool flag_nomeminit = false;
@ -258,6 +265,14 @@ struct VerilogFrontend : public Frontend {
assert_assumes_mode = true; assert_assumes_mode = true;
continue; continue;
} }
if (arg == "-debug") {
flag_dump_ast1 = true;
flag_dump_ast2 = true;
flag_dump_vlog1 = true;
flag_dump_vlog2 = true;
frontend_verilog_yydebug = true;
continue;
}
if (arg == "-dump_ast1") { if (arg == "-dump_ast1") {
flag_dump_ast1 = true; flag_dump_ast1 = true;
continue; continue;
@ -270,8 +285,12 @@ struct VerilogFrontend : public Frontend {
flag_no_dump_ptr = true; flag_no_dump_ptr = true;
continue; continue;
} }
if (arg == "-dump_vlog") { if (arg == "-dump_vlog1") {
flag_dump_vlog = true; flag_dump_vlog1 = true;
continue;
}
if (arg == "-dump_vlog2") {
flag_dump_vlog2 = true;
continue; continue;
} }
if (arg == "-dump_rtlil") { if (arg == "-dump_rtlil") {
@ -410,7 +429,7 @@ struct VerilogFrontend : public Frontend {
if (flag_nodpi) if (flag_nodpi)
error_on_dpi_function(current_ast); error_on_dpi_function(current_ast);
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
if (!flag_nopp) if (!flag_nopp)
delete lexin; delete lexin;

27
passes/opt/wreduce.cc
View File

@ -54,6 +54,7 @@ struct WreduceWorker
std::set<SigBit> work_queue_bits; std::set<SigBit> work_queue_bits;
pool<SigBit> keep_bits; pool<SigBit> keep_bits;
dict<SigBit, State> init_bits; dict<SigBit, State> init_bits;
pool<SigBit> remove_init_bits;
WreduceWorker(WreduceConfig *config, Module *module) : WreduceWorker(WreduceConfig *config, Module *module) :
config(config), module(module), mi(module) { } config(config), module(module), mi(module) { }
@ -164,6 +165,7 @@ struct WreduceWorker
{ {
if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) { if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) {
module->connect(sig_q[i], State::S0); module->connect(sig_q[i], State::S0);
remove_init_bits.insert(sig_q[i]);
sig_d.remove(i); sig_d.remove(i);
sig_q.remove(i); sig_q.remove(i);
continue; continue;
@ -171,6 +173,7 @@ struct WreduceWorker
if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) { if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) {
module->connect(sig_q[i], sig_q[i-1]); module->connect(sig_q[i], sig_q[i-1]);
remove_init_bits.insert(sig_q[i]);
sig_d.remove(i); sig_d.remove(i);
sig_q.remove(i); sig_q.remove(i);
continue; continue;
@ -178,6 +181,7 @@ struct WreduceWorker
auto info = mi.query(sig_q[i]); auto info = mi.query(sig_q[i]);
if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) { if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
remove_init_bits.insert(sig_q[i]);
sig_d.remove(i); sig_d.remove(i);
sig_q.remove(i); sig_q.remove(i);
zero_ext = false; zero_ext = false;
@ -387,13 +391,16 @@ struct WreduceWorker
void run() void run()
{ {
// create a copy as mi.sigmap will be updated as we process the module
SigMap init_attr_sigmap = mi.sigmap;
for (auto w : module->wires()) { for (auto w : module->wires()) {
if (w->get_bool_attribute("\\keep")) if (w->get_bool_attribute("\\keep"))
for (auto bit : mi.sigmap(w)) for (auto bit : mi.sigmap(w))
keep_bits.insert(bit); keep_bits.insert(bit);
if (w->attributes.count("\\init")) { if (w->attributes.count("\\init")) {
Const initval = w->attributes.at("\\init"); Const initval = w->attributes.at("\\init");
SigSpec initsig = mi.sigmap(w); SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig)); int width = std::min(GetSize(initval), GetSize(initsig));
for (int i = 0; i < width; i++) for (int i = 0; i < width; i++)
init_bits[initsig[i]] = initval[i]; init_bits[initsig[i]] = initval[i];
@ -446,6 +453,24 @@ struct WreduceWorker
module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw); module->swap_names(w, nw);
} }
if (!remove_init_bits.empty()) {
for (auto w : module->wires()) {
if (w->attributes.count("\\init")) {
Const initval = w->attributes.at("\\init");
Const new_initval(State::Sx, GetSize(w));
SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig));
for (int i = 0; i < width; i++) {
log_dump(initsig[i], remove_init_bits.count(initsig[i]));
if (!remove_init_bits.count(initsig[i]))
new_initval[i] = initval[i];
}
w->attributes.at("\\init") = new_initval;
log_dump(w->name, initval, new_initval);
}
}
}
} }
}; };

12
techlibs/xilinx/cells_xtra.sh
View File

@ -7,6 +7,7 @@ function xtract_cell_decl()
{ {
for dir in $libdir/xeclib $libdir/retarget; do for dir in $libdir/xeclib $libdir/retarget; do
[ -f $dir/$1.v ] || continue [ -f $dir/$1.v ] || continue
[ -z "$2" ] || echo $2
egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v | egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d; sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/; s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
@ -37,10 +38,10 @@ function xtract_cell_decl()
xtract_cell_decl BUFMR xtract_cell_decl BUFMR
xtract_cell_decl BUFMRCE xtract_cell_decl BUFMRCE
xtract_cell_decl BUFR xtract_cell_decl BUFR
xtract_cell_decl CAPTUREE2 xtract_cell_decl CAPTUREE2 "(* keep *)"
# xtract_cell_decl CARRY4 # xtract_cell_decl CARRY4
xtract_cell_decl CFGLUT5 xtract_cell_decl CFGLUT5
xtract_cell_decl DCIRESET xtract_cell_decl DCIRESET "(* keep *)"
xtract_cell_decl DNA_PORT xtract_cell_decl DNA_PORT
xtract_cell_decl DSP48E1 xtract_cell_decl DSP48E1
xtract_cell_decl EFUSE_USR xtract_cell_decl EFUSE_USR
@ -67,10 +68,10 @@ function xtract_cell_decl()
xtract_cell_decl IBUFDS_GTE2 xtract_cell_decl IBUFDS_GTE2
xtract_cell_decl IBUFDS_IBUFDISABLE xtract_cell_decl IBUFDS_IBUFDISABLE
xtract_cell_decl IBUFDS_INTERMDISABLE xtract_cell_decl IBUFDS_INTERMDISABLE
xtract_cell_decl ICAPE2 xtract_cell_decl ICAPE2 "(* keep *)"
xtract_cell_decl IDDR xtract_cell_decl IDDR
xtract_cell_decl IDDR_2CLK xtract_cell_decl IDDR_2CLK
xtract_cell_decl IDELAYCTRL xtract_cell_decl IDELAYCTRL "(* keep *)"
xtract_cell_decl IDELAYE2 xtract_cell_decl IDELAYE2
xtract_cell_decl IN_FIFO xtract_cell_decl IN_FIFO
xtract_cell_decl IOBUF xtract_cell_decl IOBUF
@ -112,7 +113,7 @@ function xtract_cell_decl()
xtract_cell_decl PHY_CONTROL xtract_cell_decl PHY_CONTROL
xtract_cell_decl PLLE2_ADV xtract_cell_decl PLLE2_ADV
xtract_cell_decl PLLE2_BASE xtract_cell_decl PLLE2_BASE
xtract_cell_decl PS7 xtract_cell_decl PS7 "(* keep *)"
xtract_cell_decl PULLDOWN xtract_cell_decl PULLDOWN
xtract_cell_decl PULLUP xtract_cell_decl PULLUP
xtract_cell_decl RAM128X1D xtract_cell_decl RAM128X1D
@ -137,6 +138,7 @@ function xtract_cell_decl()
#xtract_cell_decl SRL16E #xtract_cell_decl SRL16E
#xtract_cell_decl SRLC32E #xtract_cell_decl SRLC32E
xtract_cell_decl STARTUPE2 xtract_cell_decl STARTUPE2
xtract_cell_decl STARTUPE2 "(* keep *)"
xtract_cell_decl USR_ACCESSE2 xtract_cell_decl USR_ACCESSE2
xtract_cell_decl XADC xtract_cell_decl XADC
} > cells_xtra.new } > cells_xtra.new

43
techlibs/xilinx/cells_xtra.v
View File

@ -114,6 +114,7 @@ module BUFR (...);
parameter SIM_DEVICE = "7SERIES"; parameter SIM_DEVICE = "7SERIES";
endmodule endmodule
(* keep *)
module CAPTUREE2 (...); module CAPTUREE2 (...);
parameter ONESHOT = "TRUE"; parameter ONESHOT = "TRUE";
input CAP; input CAP;
@ -130,6 +131,7 @@ module CFGLUT5 (...);
input CDI, CE, CLK; input CDI, CE, CLK;
endmodule endmodule
(* keep *)
module DCIRESET (...); module DCIRESET (...);
output LOCKED; output LOCKED;
input RST; input RST;
@ -2102,6 +2104,7 @@ module IBUFDS_INTERMDISABLE (...);
input INTERMDISABLE; input INTERMDISABLE;
endmodule endmodule
(* keep *)
module ICAPE2 (...); module ICAPE2 (...);
parameter [31:0] DEVICE_ID = 32'h04244093; parameter [31:0] DEVICE_ID = 32'h04244093;
parameter ICAP_WIDTH = "X32"; parameter ICAP_WIDTH = "X32";
@ -2149,6 +2152,7 @@ module IDDR_2CLK (...);
input S; input S;
endmodule endmodule
(* keep *)
module IDELAYCTRL (...); module IDELAYCTRL (...);
parameter SIM_DEVICE = "7SERIES"; parameter SIM_DEVICE = "7SERIES";
output RDY; output RDY;
@ -3057,6 +3061,7 @@ module PLLE2_BASE (...);
input RST; input RST;
endmodule endmodule
(* keep *)
module PS7 (...); module PS7 (...);
output DMA0DAVALID; output DMA0DAVALID;
output DMA0DRREADY; output DMA0DRREADY;
@ -3688,6 +3693,17 @@ module PULLUP (...);
output O; output O;
endmodule endmodule
module RAM128X1D (...);
parameter [127:0] INIT = 128'h00000000000000000000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output DPO, SPO;
input [6:0] A;
input [6:0] DPRA;
input D;
input WCLK;
input WE;
endmodule
module RAM128X1S (...); module RAM128X1S (...);
parameter [127:0] INIT = 128'h00000000000000000000000000000000; parameter [127:0] INIT = 128'h00000000000000000000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0; parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@ -3695,25 +3711,6 @@ module RAM128X1S (...);
input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE; input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
endmodule endmodule
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input [6:0] A, DPRA
);
parameter [127:0] INIT = 128'bx;
parameter IS_WCLK_INVERTED = 0;
endmodule
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter [63:0] INIT = 64'bx;
parameter IS_WCLK_INVERTED = 0;
endmodule
module RAM256X1S (...); module RAM256X1S (...);
parameter [255:0] INIT = 256'h0; parameter [255:0] INIT = 256'h0;
parameter [0:0] IS_WCLK_INVERTED = 1'b0; parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@ -3797,6 +3794,13 @@ module RAM64M (...);
input WE; input WE;
endmodule endmodule
module RAM64X1D (...);
parameter [63:0] INIT = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output DPO, SPO;
input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
endmodule
module RAM64X1S (...); module RAM64X1S (...);
parameter [63:0] INIT = 64'h0000000000000000; parameter [63:0] INIT = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0; parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@ -3843,6 +3847,7 @@ module ROM64X1 (...);
input A0, A1, A2, A3, A4, A5; input A0, A1, A2, A3, A4, A5;
endmodule endmodule
(* keep *)
module STARTUPE2 (...); module STARTUPE2 (...);
parameter PROG_USR = "FALSE"; parameter PROG_USR = "FALSE";
parameter real SIM_CCLK_FREQ = 0.0; parameter real SIM_CCLK_FREQ = 0.0;