riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #2403 from nakengelhardt/sim_timescale 

sim -vcd: add date, version, and option for timescale
This commit is contained in:
N. Engelhardt 2020-10-22 14:01:24 +02:00 committed by GitHub
parent eb76d35e80 1c96a0b1d5
commit 3b86b5da5f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 21 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
passes/sat/sim.cc
View File

@ -22,6 +22,8 @@
#include "kernel/celltypes.h"
#include "kernel/mem.h"
#include <ctime>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -620,6 +622,7 @@ struct SimWorker : SimShared
SimInstance *top = nullptr;
std::ofstream vcdfile;
pool<IdString> clock, clockn, reset, resetn;
std::string timescale;
~SimWorker()
{
@ -631,6 +634,17 @@ struct SimWorker : SimShared
if (!vcdfile.is_open())
return;
vcdfile << stringf("$version %s $end\n", yosys_version_str);
std::time_t t = std::time(nullptr);
char mbstr[255];
if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
}
if (!timescale.empty())
vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
int id = 1;
top->write_vcd_header(vcdfile, id);
@ -770,6 +784,9 @@ struct SimPass : public Pass {
log(" -zinit\n");
log(" zero-initialize all uninitialized regs and memories\n");
log("\n");
log(" -timescale <string>\n");
log(" include the specified timescale declaration in the vcd\n");
log("\n");
log(" -n <integer>\n");
log(" number of cycles to simulate (default: 20)\n");
log("\n");
@ -820,6 +837,10 @@ struct SimPass : public Pass {
worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
continue;
}
if (args[argidx] == "-timescale" && argidx+1 < args.size()) {
worker.timescale = args[++argidx];
continue;
}
if (args[argidx] == "-a") {
worker.hide_internal = false;
continue;