mirror of https://github.com/YosysHQ/yosys.git
883 lines
21 KiB
C++
883 lines
21 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/mem.h"
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#include <ctime>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SimShared
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{
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bool debug = false;
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bool hide_internal = true;
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bool writeback = false;
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bool zinit = false;
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int rstlen = 1;
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};
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void zinit(State &v)
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{
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if (v != State::S1)
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v = State::S0;
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}
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void zinit(Const &v)
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{
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for (auto &bit : v.bits)
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zinit(bit);
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}
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struct SimInstance
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{
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SimShared *shared;
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Module *module;
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Cell *instance;
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SimInstance *parent;
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dict<Cell*, SimInstance*> children;
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SigMap sigmap;
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dict<SigBit, State> state_nets;
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dict<SigBit, pool<Cell*>> upd_cells;
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dict<SigBit, pool<Wire*>> upd_outports;
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pool<SigBit> dirty_bits;
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pool<Cell*> dirty_cells;
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pool<IdString> dirty_memories;
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pool<SimInstance*, hash_ptr_ops> dirty_children;
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struct ff_state_t
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{
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State past_clock;
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Const past_d;
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};
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struct mem_state_t
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{
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Mem *mem;
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std::vector<Const> past_wr_clk;
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std::vector<Const> past_wr_en;
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std::vector<Const> past_wr_addr;
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std::vector<Const> past_wr_data;
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Const data;
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};
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dict<Cell*, ff_state_t> ff_database;
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dict<IdString, mem_state_t> mem_database;
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pool<Cell*> formal_database;
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dict<Cell*, IdString> mem_cells;
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std::vector<Mem> memories;
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dict<Wire*, pair<int, Const>> vcd_database;
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SimInstance(SimShared *shared, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
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shared(shared), module(module), instance(instance), parent(parent), sigmap(module)
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{
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log_assert(module);
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if (parent) {
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log_assert(parent->children.count(instance) == 0);
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parent->children[instance] = this;
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}
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for (auto wire : module->wires())
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{
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(sig); i++) {
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if (state_nets.count(sig[i]) == 0)
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state_nets[sig[i]] = State::Sx;
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if (wire->port_output) {
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upd_outports[sig[i]].insert(wire);
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dirty_bits.insert(sig[i]);
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}
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}
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if (wire->attributes.count(ID::init)) {
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Const initval = wire->attributes.at(ID::init);
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for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1) {
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state_nets[sig[i]] = initval[i];
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dirty_bits.insert(sig[i]);
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}
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}
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}
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memories = Mem::get_all_memories(module);
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for (auto &mem : memories) {
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auto &mdb = mem_database[mem.memid];
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mdb.mem = &mem;
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for (auto &port : mem.wr_ports) {
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mdb.past_wr_clk.push_back(Const(State::Sx));
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mdb.past_wr_en.push_back(Const(State::Sx, GetSize(port.en)));
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mdb.past_wr_addr.push_back(Const(State::Sx, GetSize(port.addr)));
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mdb.past_wr_data.push_back(Const(State::Sx, GetSize(port.data)));
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}
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mdb.data = mem.get_init_data();
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}
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for (auto cell : module->cells())
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{
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Module *mod = module->design->module(cell->type);
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if (mod != nullptr) {
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dirty_children.insert(new SimInstance(shared, mod, cell, this));
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}
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for (auto &port : cell->connections()) {
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if (cell->input(port.first))
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for (auto bit : sigmap(port.second)) {
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upd_cells[bit].insert(cell);
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// Make sure cell inputs connected to constants are updated in the first cycle
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if (bit.wire == nullptr)
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dirty_bits.insert(bit);
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}
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}
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if (cell->type.in(ID($dff))) {
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ff_state_t ff;
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ff.past_clock = State::Sx;
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ff.past_d = Const(State::Sx, cell->getParam(ID::WIDTH).as_int());
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ff_database[cell] = ff;
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}
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if (cell->type.in(ID($mem), ID($meminit), ID($memwr), ID($memrd)))
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{
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mem_cells[cell] = cell->parameters.at(ID::MEMID).decode_string();
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}
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if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
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formal_database.insert(cell);
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}
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}
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if (shared->zinit)
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{
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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zinit(ff.past_d);
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SigSpec qsig = cell->getPort(ID::Q);
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Const qdata = get_state(qsig);
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zinit(qdata);
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set_state(qsig, qdata);
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}
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for (auto &it : mem_database) {
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mem_state_t &mem = it.second;
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for (auto &val : mem.past_wr_en)
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zinit(val);
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zinit(mem.data);
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}
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}
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}
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~SimInstance()
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{
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for (auto child : children)
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delete child.second;
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}
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IdString name() const
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{
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if (instance != nullptr)
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return instance->name;
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return module->name;
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}
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std::string hiername() const
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{
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if (instance != nullptr)
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return parent->hiername() + "." + log_id(instance->name);
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return log_id(module->name);
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}
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Const get_state(SigSpec sig)
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{
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Const value;
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for (auto bit : sigmap(sig))
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if (bit.wire == nullptr)
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value.bits.push_back(bit.data);
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else if (state_nets.count(bit))
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value.bits.push_back(state_nets.at(bit));
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else
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value.bits.push_back(State::Sz);
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if (shared->debug)
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log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
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return value;
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}
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bool set_state(SigSpec sig, Const value)
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{
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bool did_something = false;
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sig = sigmap(sig);
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log_assert(GetSize(sig) <= GetSize(value));
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for (int i = 0; i < GetSize(sig); i++)
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if (state_nets.at(sig[i]) != value[i]) {
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state_nets.at(sig[i]) = value[i];
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dirty_bits.insert(sig[i]);
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did_something = true;
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}
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if (shared->debug)
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log("[%s] set %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
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return did_something;
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}
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void update_cell(Cell *cell)
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{
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if (ff_database.count(cell))
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return;
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if (formal_database.count(cell))
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return;
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if (mem_cells.count(cell))
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{
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dirty_memories.insert(mem_cells[cell]);
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return;
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}
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if (children.count(cell))
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{
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auto child = children.at(cell);
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for (auto &conn: cell->connections())
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if (cell->input(conn.first)) {
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Const value = get_state(conn.second);
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child->set_state(child->module->wire(conn.first), value);
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}
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dirty_children.insert(child);
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return;
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}
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if (yosys_celltypes.cell_evaluable(cell->type))
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{
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RTLIL::SigSpec sig_a, sig_b, sig_c, sig_d, sig_s, sig_y;
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bool has_a, has_b, has_c, has_d, has_s, has_y;
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has_a = cell->hasPort(ID::A);
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has_b = cell->hasPort(ID::B);
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has_c = cell->hasPort(ID::C);
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has_d = cell->hasPort(ID::D);
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has_s = cell->hasPort(ID::S);
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has_y = cell->hasPort(ID::Y);
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if (has_a) sig_a = cell->getPort(ID::A);
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if (has_b) sig_b = cell->getPort(ID::B);
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if (has_c) sig_c = cell->getPort(ID::C);
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if (has_d) sig_d = cell->getPort(ID::D);
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if (has_s) sig_s = cell->getPort(ID::S);
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if (has_y) sig_y = cell->getPort(ID::Y);
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if (shared->debug)
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log("[%s] eval %s (%s)\n", hiername().c_str(), log_id(cell), log_id(cell->type));
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// Simple (A -> Y) and (A,B -> Y) cells
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if (has_a && !has_c && !has_d && !has_s && has_y) {
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set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b)));
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return;
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}
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// (A,B,C -> Y) cells
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if (has_a && has_b && has_c && !has_d && !has_s && has_y) {
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set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c)));
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return;
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}
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// (A,B,S -> Y) cells
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if (has_a && has_b && !has_c && !has_d && has_s && has_y) {
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set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s)));
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return;
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}
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log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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return;
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}
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log_error("Unsupported cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
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}
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void update_memory(IdString id) {
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auto &mdb = mem_database[id];
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auto &mem = *mdb.mem;
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for (int port_idx = 0; port_idx < GetSize(mem.rd_ports); port_idx++)
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{
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auto &port = mem.rd_ports[port_idx];
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Const addr = get_state(port.addr);
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Const data = Const(State::Sx, mem.width);
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if (port.clk_enable)
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log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(mem.memid));
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if (addr.is_fully_def()) {
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int index = addr.as_int() - mem.start_offset;
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if (index >= 0 && index < mem.size)
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data = mdb.data.extract(index*mem.width, mem.width);
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}
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set_state(port.data, data);
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}
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}
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void update_ph1()
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{
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pool<Cell*> queue_cells;
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pool<Wire*> queue_outports;
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queue_cells.swap(dirty_cells);
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while (1)
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{
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for (auto bit : dirty_bits)
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{
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if (upd_cells.count(bit))
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for (auto cell : upd_cells.at(bit))
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queue_cells.insert(cell);
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if (upd_outports.count(bit) && parent != nullptr)
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for (auto wire : upd_outports.at(bit))
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queue_outports.insert(wire);
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}
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dirty_bits.clear();
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if (!queue_cells.empty())
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{
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for (auto cell : queue_cells)
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update_cell(cell);
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queue_cells.clear();
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continue;
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}
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for (auto &memid : dirty_memories)
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update_memory(memid);
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dirty_memories.clear();
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for (auto wire : queue_outports)
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if (instance->hasPort(wire->name)) {
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Const value = get_state(wire);
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parent->set_state(instance->getPort(wire->name), value);
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}
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queue_outports.clear();
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for (auto child : dirty_children)
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child->update_ph1();
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dirty_children.clear();
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if (dirty_bits.empty())
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break;
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}
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}
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bool update_ph2()
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{
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bool did_something = false;
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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if (cell->type.in(ID($dff)))
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{
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bool clkpol = cell->getParam(ID::CLK_POLARITY).as_bool();
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State current_clock = get_state(cell->getPort(ID::CLK))[0];
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if (clkpol ? (ff.past_clock == State::S1 || current_clock != State::S1) :
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(ff.past_clock == State::S0 || current_clock != State::S0))
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continue;
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if (set_state(cell->getPort(ID::Q), ff.past_d))
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did_something = true;
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}
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}
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for (auto &it : mem_database)
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{
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mem_state_t &mdb = it.second;
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auto &mem = *mdb.mem;
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for (int port_idx = 0; port_idx < GetSize(mem.wr_ports); port_idx++)
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{
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auto &port = mem.wr_ports[port_idx];
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Const addr, data, enable;
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if (!port.clk_enable)
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{
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addr = get_state(port.addr);
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data = get_state(port.data);
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enable = get_state(port.en);
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}
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else
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{
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if (port.clk_polarity ?
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(mdb.past_wr_clk[port_idx] == State::S1 || get_state(port.clk) != State::S1) :
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(mdb.past_wr_clk[port_idx] == State::S0 || get_state(port.clk) != State::S0))
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continue;
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addr = mdb.past_wr_addr[port_idx];
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data = mdb.past_wr_data[port_idx];
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enable = mdb.past_wr_en[port_idx];
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}
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if (addr.is_fully_def())
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{
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int index = addr.as_int() - mem.start_offset;
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if (index >= 0 && index < mem.size)
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for (int i = 0; i < mem.width; i++)
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if (enable[i] == State::S1 && mdb.data.bits.at(index*mem.width+i) != data[i]) {
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mdb.data.bits.at(index*mem.width+i) = data[i];
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dirty_memories.insert(mem.memid);
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did_something = true;
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}
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}
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}
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}
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for (auto it : children)
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if (it.second->update_ph2()) {
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dirty_children.insert(it.second);
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did_something = true;
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}
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return did_something;
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}
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void update_ph3()
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{
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for (auto &it : ff_database)
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{
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Cell *cell = it.first;
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ff_state_t &ff = it.second;
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if (cell->type.in(ID($dff))) {
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ff.past_clock = get_state(cell->getPort(ID::CLK))[0];
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ff.past_d = get_state(cell->getPort(ID::D));
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}
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}
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for (auto &it : mem_database)
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{
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mem_state_t &mem = it.second;
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for (int i = 0; i < GetSize(mem.mem->wr_ports); i++) {
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auto &port = mem.mem->wr_ports[i];
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mem.past_wr_clk[i] = get_state(port.clk);
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mem.past_wr_en[i] = get_state(port.en);
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mem.past_wr_addr[i] = get_state(port.addr);
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mem.past_wr_data[i] = get_state(port.data);
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}
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}
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for (auto cell : formal_database)
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{
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string label = log_id(cell);
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if (cell->attributes.count(ID::src))
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label = cell->attributes.at(ID::src).decode_string();
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State a = get_state(cell->getPort(ID::A))[0];
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State en = get_state(cell->getPort(ID::EN))[0];
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if (cell->type == ID($cover) && en == State::S1 && a != State::S1)
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log("Cover %s.%s (%s) reached.\n", hiername().c_str(), log_id(cell), label.c_str());
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if (cell->type == ID($assume) && en == State::S1 && a != State::S1)
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log("Assumption %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
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if (cell->type == ID($assert) && en == State::S1 && a != State::S1)
|
|
log_warning("Assert %s.%s (%s) failed.\n", hiername().c_str(), log_id(cell), label.c_str());
|
|
}
|
|
|
|
for (auto it : children)
|
|
it.second->update_ph3();
|
|
}
|
|
|
|
void writeback(pool<Module*> &wbmods)
|
|
{
|
|
if (wbmods.count(module))
|
|
log_error("Instance %s of module %s is not unique: Writeback not possible. (Fix by running 'uniquify'.)\n", hiername().c_str(), log_id(module));
|
|
|
|
wbmods.insert(module);
|
|
|
|
for (auto wire : module->wires())
|
|
wire->attributes.erase(ID::init);
|
|
|
|
for (auto &it : ff_database)
|
|
{
|
|
Cell *cell = it.first;
|
|
SigSpec sig_q = cell->getPort(ID::Q);
|
|
Const initval = get_state(sig_q);
|
|
|
|
for (int i = 0; i < GetSize(sig_q); i++)
|
|
{
|
|
Wire *w = sig_q[i].wire;
|
|
|
|
if (w->attributes.count(ID::init) == 0)
|
|
w->attributes[ID::init] = Const(State::Sx, GetSize(w));
|
|
|
|
w->attributes[ID::init][sig_q[i].offset] = initval[i];
|
|
}
|
|
}
|
|
|
|
for (auto &it : mem_database)
|
|
{
|
|
mem_state_t &mem = it.second;
|
|
mem.mem->clear_inits();
|
|
MemInit minit;
|
|
minit.addr = mem.mem->start_offset;
|
|
minit.data = mem.data;
|
|
mem.mem->inits.push_back(minit);
|
|
mem.mem->emit();
|
|
}
|
|
|
|
for (auto it : children)
|
|
it.second->writeback(wbmods);
|
|
}
|
|
|
|
void write_vcd_header(std::ofstream &f, int &id)
|
|
{
|
|
f << stringf("$scope module %s $end\n", log_id(name()));
|
|
|
|
for (auto wire : module->wires())
|
|
{
|
|
if (shared->hide_internal && wire->name[0] == '$')
|
|
continue;
|
|
|
|
f << stringf("$var wire %d n%d %s%s $end\n", GetSize(wire), id, wire->name[0] == '$' ? "\\" : "", log_id(wire));
|
|
vcd_database[wire] = make_pair(id++, Const());
|
|
}
|
|
|
|
for (auto child : children)
|
|
child.second->write_vcd_header(f, id);
|
|
|
|
f << stringf("$upscope $end\n");
|
|
}
|
|
|
|
void write_vcd_step(std::ofstream &f)
|
|
{
|
|
for (auto &it : vcd_database)
|
|
{
|
|
Wire *wire = it.first;
|
|
Const value = get_state(wire);
|
|
int id = it.second.first;
|
|
|
|
if (it.second.second == value)
|
|
continue;
|
|
|
|
it.second.second = value;
|
|
|
|
f << "b";
|
|
for (int i = GetSize(value)-1; i >= 0; i--) {
|
|
switch (value[i]) {
|
|
case State::S0: f << "0"; break;
|
|
case State::S1: f << "1"; break;
|
|
case State::Sx: f << "x"; break;
|
|
default: f << "z";
|
|
}
|
|
}
|
|
|
|
f << stringf(" n%d\n", id);
|
|
}
|
|
|
|
for (auto child : children)
|
|
child.second->write_vcd_step(f);
|
|
}
|
|
};
|
|
|
|
struct SimWorker : SimShared
|
|
{
|
|
SimInstance *top = nullptr;
|
|
std::ofstream vcdfile;
|
|
pool<IdString> clock, clockn, reset, resetn;
|
|
std::string timescale;
|
|
|
|
~SimWorker()
|
|
{
|
|
delete top;
|
|
}
|
|
|
|
void write_vcd_header()
|
|
{
|
|
if (!vcdfile.is_open())
|
|
return;
|
|
|
|
vcdfile << stringf("$version %s $end\n", yosys_version_str);
|
|
|
|
std::time_t t = std::time(nullptr);
|
|
char mbstr[255];
|
|
if (std::strftime(mbstr, sizeof(mbstr), "%c", std::localtime(&t))) {
|
|
vcdfile << stringf("$date ") << mbstr << stringf(" $end\n");
|
|
}
|
|
|
|
if (!timescale.empty())
|
|
vcdfile << stringf("$timescale %s $end\n", timescale.c_str());
|
|
|
|
int id = 1;
|
|
top->write_vcd_header(vcdfile, id);
|
|
|
|
vcdfile << stringf("$enddefinitions $end\n");
|
|
}
|
|
|
|
void write_vcd_step(int t)
|
|
{
|
|
if (!vcdfile.is_open())
|
|
return;
|
|
|
|
vcdfile << stringf("#%d\n", t);
|
|
top->write_vcd_step(vcdfile);
|
|
}
|
|
|
|
void update()
|
|
{
|
|
while (1)
|
|
{
|
|
if (debug)
|
|
log("\n-- ph1 --\n");
|
|
|
|
top->update_ph1();
|
|
|
|
if (debug)
|
|
log("\n-- ph2 --\n");
|
|
|
|
if (!top->update_ph2())
|
|
break;
|
|
}
|
|
|
|
if (debug)
|
|
log("\n-- ph3 --\n");
|
|
|
|
top->update_ph3();
|
|
}
|
|
|
|
void set_inports(pool<IdString> ports, State value)
|
|
{
|
|
for (auto portname : ports)
|
|
{
|
|
Wire *w = top->module->wire(portname);
|
|
|
|
if (w == nullptr)
|
|
log_error("Can't find port %s on module %s.\n", log_id(portname), log_id(top->module));
|
|
|
|
top->set_state(w, value);
|
|
}
|
|
}
|
|
|
|
void run(Module *topmod, int numcycles)
|
|
{
|
|
log_assert(top == nullptr);
|
|
top = new SimInstance(this, topmod);
|
|
|
|
if (debug)
|
|
log("\n===== 0 =====\n");
|
|
else
|
|
log("Simulating cycle 0.\n");
|
|
|
|
set_inports(reset, State::S1);
|
|
set_inports(resetn, State::S0);
|
|
|
|
set_inports(clock, State::Sx);
|
|
set_inports(clockn, State::Sx);
|
|
|
|
update();
|
|
|
|
write_vcd_header();
|
|
write_vcd_step(0);
|
|
|
|
for (int cycle = 0; cycle < numcycles; cycle++)
|
|
{
|
|
if (debug)
|
|
log("\n===== %d =====\n", 10*cycle + 5);
|
|
|
|
set_inports(clock, State::S0);
|
|
set_inports(clockn, State::S1);
|
|
|
|
update();
|
|
write_vcd_step(10*cycle + 5);
|
|
|
|
if (debug)
|
|
log("\n===== %d =====\n", 10*cycle + 10);
|
|
else
|
|
log("Simulating cycle %d.\n", cycle+1);
|
|
|
|
set_inports(clock, State::S1);
|
|
set_inports(clockn, State::S0);
|
|
|
|
if (cycle+1 == rstlen) {
|
|
set_inports(reset, State::S0);
|
|
set_inports(resetn, State::S1);
|
|
}
|
|
|
|
update();
|
|
write_vcd_step(10*cycle + 10);
|
|
}
|
|
|
|
write_vcd_step(10*numcycles + 2);
|
|
|
|
if (writeback) {
|
|
pool<Module*> wbmods;
|
|
top->writeback(wbmods);
|
|
}
|
|
}
|
|
};
|
|
|
|
struct SimPass : public Pass {
|
|
SimPass() : Pass("sim", "simulate the circuit") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" sim [options] [top-level]\n");
|
|
log("\n");
|
|
log("This command simulates the circuit using the given top-level module.\n");
|
|
log("\n");
|
|
log(" -vcd <filename>\n");
|
|
log(" write the simulation results to the given VCD file\n");
|
|
log("\n");
|
|
log(" -clock <portname>\n");
|
|
log(" name of top-level clock input\n");
|
|
log("\n");
|
|
log(" -clockn <portname>\n");
|
|
log(" name of top-level clock input (inverse polarity)\n");
|
|
log("\n");
|
|
log(" -reset <portname>\n");
|
|
log(" name of top-level reset input (active high)\n");
|
|
log("\n");
|
|
log(" -resetn <portname>\n");
|
|
log(" name of top-level inverted reset input (active low)\n");
|
|
log("\n");
|
|
log(" -rstlen <integer>\n");
|
|
log(" number of cycles reset should stay active (default: 1)\n");
|
|
log("\n");
|
|
log(" -zinit\n");
|
|
log(" zero-initialize all uninitialized regs and memories\n");
|
|
log("\n");
|
|
log(" -timescale <string>\n");
|
|
log(" include the specified timescale declaration in the vcd\n");
|
|
log("\n");
|
|
log(" -n <integer>\n");
|
|
log(" number of cycles to simulate (default: 20)\n");
|
|
log("\n");
|
|
log(" -a\n");
|
|
log(" include all nets in VCD output, not just those with public names\n");
|
|
log("\n");
|
|
log(" -w\n");
|
|
log(" writeback mode: use final simulation state as new init state\n");
|
|
log("\n");
|
|
log(" -d\n");
|
|
log(" enable debug output\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
SimWorker worker;
|
|
int numcycles = 20;
|
|
|
|
log_header(design, "Executing SIM pass (simulate the circuit).\n");
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-vcd" && argidx+1 < args.size()) {
|
|
worker.vcdfile.open(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-n" && argidx+1 < args.size()) {
|
|
numcycles = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {
|
|
worker.rstlen = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-clock" && argidx+1 < args.size()) {
|
|
worker.clock.insert(RTLIL::escape_id(args[++argidx]));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-clockn" && argidx+1 < args.size()) {
|
|
worker.clockn.insert(RTLIL::escape_id(args[++argidx]));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-reset" && argidx+1 < args.size()) {
|
|
worker.reset.insert(RTLIL::escape_id(args[++argidx]));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-resetn" && argidx+1 < args.size()) {
|
|
worker.resetn.insert(RTLIL::escape_id(args[++argidx]));
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-timescale" && argidx+1 < args.size()) {
|
|
worker.timescale = args[++argidx];
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-a") {
|
|
worker.hide_internal = false;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-d") {
|
|
worker.debug = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-w") {
|
|
worker.writeback = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-zinit") {
|
|
worker.zinit = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
Module *top_mod = nullptr;
|
|
|
|
if (design->full_selection()) {
|
|
top_mod = design->top_module();
|
|
|
|
if (!top_mod)
|
|
log_cmd_error("Design has no top module, use the 'hierarchy' command to specify one.\n");
|
|
} else {
|
|
auto mods = design->selected_whole_modules();
|
|
if (GetSize(mods) != 1)
|
|
log_cmd_error("Only one top module must be selected.\n");
|
|
top_mod = mods.front();
|
|
}
|
|
|
|
worker.run(top_mod, numcycles);
|
|
}
|
|
} SimPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|