riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' into mwk/xilinx_bufgmap

This commit is contained in:
Eddie Hung 2019-08-23 11:24:19 -07:00
parent 0d0ad15898 509c353fe9
commit 20f4d191b5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/xilinx/cells_sim.v
View File

@ -343,7 +343,7 @@ module RAM64X1D (
(* clkbuf_sink *) (* clkbuf_sink *)
input WCLK, input WCLK,
(* abc_scc_break *) (* abc_scc_break *)
input WE, input WE,
input A0, A1, A2, A3, A4, A5, input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
); );