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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

This commit is contained in:
Eddie Hung 2020-01-15 16:42:16 -08:00
parent d6da9c0c0f 2bda51ac34
commit 03ce2c72bb
3 changed files with 16 additions and 3 deletions
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4
frontends/aiger/aigerparse.cc
View File

@ -922,9 +922,9 @@ void AigerReader::post_process()
if (cell->type != "$lut") continue; if (cell->type != "$lut") continue;
auto y_port = cell->getPort("\\Y").as_bit(); auto y_port = cell->getPort("\\Y").as_bit();
if (y_port.wire->width == 1) if (y_port.wire->width == 1)
module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str())); module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
else else
module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset)); module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset));
} }
} }

2
techlibs/xilinx/synth_xilinx.cc
View File

@ -562,7 +562,7 @@ struct SynthXilinxPass : public ScriptPass
if (active_design->scratchpad.count(k)) if (active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
else else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
if (nowidelut) if (nowidelut)
abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
else else

13
tests/techmap/abc9.ys
View File

@ -52,6 +52,7 @@ equiv_opt -assert abc9 -lut 4
design -load postopt design -load postopt
select -assert-count 2 t:$lut select -assert-count 2 t:$lut
design -reset design -reset
read_verilog -icells <<EOT read_verilog -icells <<EOT
module top(input a, b, output o); module top(input a, b, output o);
@ -66,3 +67,15 @@ equiv_opt -assert abc9 -lut 4
design -load postopt design -load postopt
select -assert-count 1 t:$lut select -assert-count 1 t:$lut
select -assert-count 1 t:$_AND_ select -assert-count 1 t:$_AND_
design -reset
read_verilog -icells <<EOT
module top(input a, b, output o);
assign o = ~(a & b);
endmodule
EOT
abc9 -lut 4
clean
select -assert-count 1 t:$lut
select -assert-none t:$lut t:* %D