From 36d1a2c60ff8179d9cfbdb1ae0ca5dd5d883991a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 11:34:40 -0800
Subject: [PATCH 1/3] synth_xilinx: fix default W value for non-xc7

---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index d916093dc..b86484e71 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -562,7 +562,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (active_design->scratchpad.count(k))
 					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
 				else
-					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
+					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
 				if (nowidelut)
 					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
 				else

From 05c8858a907f0f188f1687ede260c2e1a97efe38 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 15 Jan 2020 14:31:32 -0800
Subject: [PATCH 2/3] read_aiger: $lut prefix in front

---
 frontends/aiger/aigerparse.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f6b2a639d..a4b1e6fec 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1001,9 +1001,9 @@ void AigerReader::post_process()
 		if (cell->type != "$lut") continue;
 		auto y_port = cell->getPort("\\Y").as_bit();
 		if (y_port.wire->width == 1)
-			module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
+			module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
 		else
-			module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
+			module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset));
 	}
 }
 

From 5918ede9bd7568d5a5156f20fdc4ce215d4968f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 15 Jan 2020 14:36:05 -0800
Subject: [PATCH 3/3] abc9: aAdd test to check $_NOT_s are absorbed

---
 tests/techmap/abc9.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys
index 20f263da8..62b5dfef6 100644
--- a/tests/techmap/abc9.ys
+++ b/tests/techmap/abc9.ys
@@ -38,3 +38,15 @@ abc9 -lut 4
 design -load gold
 scratchpad -copy abc9.script.flow3 abc9.script
 abc9 -lut 4
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, b, output o);
+assign o = ~(a & b);
+endmodule
+EOT
+abc9 -lut 4
+clean
+select -assert-count 1 t:$lut
+select -assert-none t:$lut t:* %D