yosys/techlibs/xilinx/xc6s_brams.txt


bram $__XILINX_RAMB8BWER_SDP
  init 1
  abits 8
  dbits 36
  groups 2
  ports  1 1
  wrmode 0 1
  enable 1 4
  transp 0 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB16BWER_TDP
  init 1
  abits  9     @a9d36
  dbits 36     @a9d36
  abits 10     @a10d18
  dbits 18     @a10d18
  abits 11     @a11d9
  dbits  9     @a11d9
  abits 12     @a12d4
  dbits  4     @a12d4
  abits 13     @a13d2
  dbits  2     @a13d2
  abits 14     @a14d1
  dbits  1     @a14d1
  groups 2
  ports  1 1
  wrmode 0 1
  enable 1 4   @a9d36
  enable 1 2   @a10d18
  enable 1 1   @a11d9 @a12d4 @a13d2 @a14d1
  transp 0 0
  clocks 2 3
  clkpol 2 3
endbram

bram $__XILINX_RAMB8BWER_TDP
  init 1
  abits  9     @a9d18
  dbits 18     @a9d18
  abits 10     @a10d9
  dbits  9     @a10d9
  abits 11     @a11d4
  dbits  4     @a11d4
  abits 12     @a12d2
  dbits  2     @a12d2
  abits 13     @a13d1
  dbits  1     @a13d1
  groups 2
  ports  1 1
  wrmode 0 1
  enable 1 2   @a9d18
  enable 1 1   @a10d9 @a11d4 @a12d2 @a13d1
  transp 0 0
  clocks 2 3
  clkpol 2 3
endbram

match $__XILINX_RAMB8BWER_SDP
  min bits 4096
  min efficiency 5
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB16BWER_TDP
  min bits 4096
  min efficiency 5
  shuffle_enable B
  make_transp
  or_next_if_better
endmatch

match $__XILINX_RAMB8BWER_TDP
  min bits 4096
  min efficiency 5
  shuffle_enable B
  make_transp
endmatch
Added memory_bram (not functional yet) 2014-12-31 09:53:53 -06:00
synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`bram $__XILINX_RAMB8BWER_SDP`
Added support for initialized xilinx brams 2015-04-06 10:07:10 -05:00			`init 1`
synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`abits 8`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`dbits 36`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
Added read-enable to memory model 2015-09-25 05:23:11 -05:00			`enable 1 4`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`transp 0 0`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`clocks 2 3`
			`clkpol 2 3`
			`endbram`

synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`bram $__XILINX_RAMB16BWER_TDP`
Added support for initialized xilinx brams 2015-04-06 10:07:10 -05:00			`init 1`
synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`abits 9 @a9d36`
			`dbits 36 @a9d36`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`abits 10 @a10d18`
			`dbits 18 @a10d18`
			`abits 11 @a11d9`
			`dbits 9 @a11d9`
			`abits 12 @a12d4`
			`dbits 4 @a12d4`
			`abits 13 @a13d2`
			`dbits 2 @a13d2`
			`abits 14 @a14d1`
			`dbits 1 @a14d1`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`enable 1 4 @a9d36`
Added read-enable to memory model 2015-09-25 05:23:11 -05:00			`enable 1 2 @a10d18`
			`enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`transp 0 0`
Towards Xilinx bram support 2015-01-04 07:23:30 -06:00			`clocks 2 3`
			`clkpol 2 3`
			`endbram`

synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`bram $__XILINX_RAMB8BWER_TDP`
			`init 1`
			`abits 9 @a9d18`
			`dbits 18 @a9d18`
			`abits 10 @a10d9`
			`dbits 9 @a10d9`
			`abits 11 @a11d4`
			`dbits 4 @a11d4`
			`abits 12 @a12d2`
			`dbits 2 @a12d2`
			`abits 13 @a13d1`
			`dbits 1 @a13d1`
			`groups 2`
			`ports 1 1`
			`wrmode 0 1`
			`enable 1 2 @a9d18`
			`enable 1 1 @a10d9 @a11d4 @a12d2 @a13d1`
			`transp 0 0`
			`clocks 2 3`
			`clkpol 2 3`
			`endbram`
Towards Xilinx bram support 2015-01-06 08:26:33 -06:00
synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`match $__XILINX_RAMB8BWER_SDP`
Towards Xilinx bram support 2015-01-06 08:26:33 -06:00			`min bits 4096`
			`min efficiency 5`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`shuffle_enable B`
Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`make_transp`
			`or_next_if_better`
			`endmatch`

synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`match $__XILINX_RAMB16BWER_TDP`
Various cleanups in xilinx techlib 2015-01-18 12:43:54 -06:00			`min bits 4096`
			`min efficiency 5`
			`shuffle_enable B`
			`make_transp`
Towards Xilinx bram support 2015-01-06 16:21:52 -06:00			`or_next_if_better`
Added memory_bram (not functional yet) 2014-12-31 09:53:53 -06:00			`endmatch`

synth_xilinx: Initial Spartan 6 block RAM inference support. 2019-07-02 07:28:35 -05:00			`match $__XILINX_RAMB8BWER_TDP`
Towards Xilinx bram support 2015-01-06 16:21:52 -06:00			`min bits 4096`
			`min efficiency 5`
Refactoring of memory_bram and xilinx brams 2015-01-18 12:05:29 -06:00			`shuffle_enable B`
			`make_transp`
Towards Xilinx bram support 2015-01-06 16:21:52 -06:00			`endmatch`
Fixed trailing whitespaces 2015-07-02 04:14:30 -05:00