yosys/manual/PRESENTATION_ExSyn/proc_01.v

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module test(input D, C, R, output reg Q);
    always @(posedge C, posedge R)
        if (R)
	    Q <= 0;
	else
	    Q <= D;
endmodule
presentation progress 2014-02-02 15:26:26 -06:00			`module test(input D, C, R, output reg Q);`
presentation progress 2014-02-02 10:57:14 -06:00			`always @(posedge C, posedge R)`
			`if (R)`
presentation progress 2014-02-02 15:26:26 -06:00			`Q <= 0;`
presentation progress 2014-02-02 10:57:14 -06:00			`else`
			`Q <= D;`
			`endmodule`