2015-06-09 02:54:22 -05:00
|
|
|
/*
|
|
|
|
* yosys -- Yosys Open SYnthesis Suite
|
|
|
|
*
|
2021-06-07 17:39:36 -05:00
|
|
|
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
|
2015-07-02 04:14:30 -05:00
|
|
|
*
|
2015-06-09 02:54:22 -05:00
|
|
|
* Permission to use, copy, modify, and/or distribute this software for any
|
|
|
|
* purpose with or without fee is hereby granted, provided that the above
|
|
|
|
* copyright notice and this permission notice appear in all copies.
|
2015-07-02 04:14:30 -05:00
|
|
|
*
|
2015-06-09 02:54:22 -05:00
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
|
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
|
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
|
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
|
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
|
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
|
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "kernel/cellaigs.h"
|
|
|
|
|
|
|
|
YOSYS_NAMESPACE_BEGIN
|
|
|
|
|
2015-06-10 16:00:12 -05:00
|
|
|
AigNode::AigNode()
|
|
|
|
{
|
|
|
|
portbit = -1;
|
|
|
|
inverter = false;
|
|
|
|
left_parent = -1;
|
|
|
|
right_parent = -1;
|
|
|
|
}
|
|
|
|
|
2015-06-09 02:54:22 -05:00
|
|
|
bool AigNode::operator==(const AigNode &other) const
|
|
|
|
{
|
|
|
|
if (portname != other.portname) return false;
|
|
|
|
if (portbit != other.portbit) return false;
|
|
|
|
if (inverter != other.inverter) return false;
|
|
|
|
if (left_parent != other.left_parent) return false;
|
|
|
|
if (right_parent != other.right_parent) return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int AigNode::hash() const
|
|
|
|
{
|
|
|
|
unsigned int h = mkhash_init;
|
|
|
|
h = mkhash(portname.hash(), portbit);
|
|
|
|
h = mkhash(h, inverter);
|
|
|
|
h = mkhash(h, left_parent);
|
|
|
|
h = mkhash(h, right_parent);
|
|
|
|
return h;
|
|
|
|
}
|
|
|
|
|
2015-06-10 01:13:56 -05:00
|
|
|
bool Aig::operator==(const Aig &other) const
|
|
|
|
{
|
|
|
|
return name == other.name;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int Aig::hash() const
|
|
|
|
{
|
|
|
|
return hash_ops<std::string>::hash(name);
|
|
|
|
}
|
|
|
|
|
2015-06-09 02:54:22 -05:00
|
|
|
struct AigMaker
|
|
|
|
{
|
|
|
|
Aig *aig;
|
2015-06-09 15:33:26 -05:00
|
|
|
Cell *cell;
|
2015-06-09 02:54:22 -05:00
|
|
|
idict<AigNode> aig_indices;
|
|
|
|
|
2015-06-09 15:33:26 -05:00
|
|
|
int the_true_node;
|
|
|
|
int the_false_node;
|
2015-06-09 02:54:22 -05:00
|
|
|
|
2015-06-09 15:33:26 -05:00
|
|
|
AigMaker(Aig *aig, Cell *cell) : aig(aig), cell(cell)
|
|
|
|
{
|
|
|
|
the_true_node = -1;
|
|
|
|
the_false_node = -1;
|
|
|
|
}
|
|
|
|
|
2015-06-10 16:00:12 -05:00
|
|
|
int node2index(const AigNode &node)
|
2015-06-09 02:54:22 -05:00
|
|
|
{
|
2015-06-10 16:00:12 -05:00
|
|
|
if (node.left_parent > node.right_parent) {
|
|
|
|
AigNode n(node);
|
|
|
|
std::swap(n.left_parent, n.right_parent);
|
|
|
|
return node2index(n);
|
|
|
|
}
|
2015-06-09 15:33:26 -05:00
|
|
|
|
|
|
|
if (!aig_indices.count(node)) {
|
|
|
|
aig_indices.expect(node, GetSize(aig->nodes));
|
|
|
|
aig->nodes.push_back(node);
|
|
|
|
}
|
|
|
|
|
|
|
|
return aig_indices.at(node);
|
|
|
|
}
|
|
|
|
|
2015-06-10 16:00:12 -05:00
|
|
|
int bool_node(bool value)
|
|
|
|
{
|
|
|
|
AigNode node;
|
|
|
|
node.inverter = value;
|
|
|
|
return node2index(node);
|
|
|
|
}
|
|
|
|
|
2015-06-09 15:33:26 -05:00
|
|
|
int inport(IdString portname, int portbit = 0, bool inverter = false)
|
|
|
|
{
|
|
|
|
if (portbit >= GetSize(cell->getPort(portname))) {
|
|
|
|
if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
|
|
|
|
return inport(portname, GetSize(cell->getPort(portname))-1, inverter);
|
2015-06-10 00:16:30 -05:00
|
|
|
return bool_node(inverter);
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
|
|
|
|
2015-06-09 02:54:22 -05:00
|
|
|
AigNode node;
|
|
|
|
node.portname = portname;
|
|
|
|
node.portbit = portbit;
|
|
|
|
node.inverter = inverter;
|
2015-06-10 16:00:12 -05:00
|
|
|
return node2index(node);
|
2015-06-09 02:54:22 -05:00
|
|
|
}
|
|
|
|
|
2015-06-11 03:48:16 -05:00
|
|
|
vector<int> inport_vec(IdString portname, int width)
|
|
|
|
{
|
|
|
|
vector<int> vec;
|
|
|
|
for (int i = 0; i < width; i++)
|
|
|
|
vec.push_back(inport(portname, i));
|
|
|
|
return vec;
|
|
|
|
}
|
|
|
|
|
2015-06-09 15:33:26 -05:00
|
|
|
int not_inport(IdString portname, int portbit = 0)
|
2015-06-09 02:54:22 -05:00
|
|
|
{
|
2015-06-09 15:33:26 -05:00
|
|
|
return inport(portname, portbit, true);
|
|
|
|
}
|
|
|
|
|
2015-06-10 16:00:12 -05:00
|
|
|
int not_gate(int A)
|
|
|
|
{
|
|
|
|
AigNode node(aig_indices[A]);
|
|
|
|
node.outports.clear();
|
|
|
|
node.inverter = !node.inverter;
|
|
|
|
return node2index(node);
|
|
|
|
}
|
|
|
|
|
|
|
|
int and_gate(int A, int B, bool inverter = false)
|
2015-06-09 15:33:26 -05:00
|
|
|
{
|
2015-06-10 16:00:12 -05:00
|
|
|
if (A == B)
|
2015-06-11 03:48:16 -05:00
|
|
|
return inverter ? not_gate(A) : A;
|
2015-06-10 16:00:12 -05:00
|
|
|
|
|
|
|
const AigNode &nA = aig_indices[A];
|
|
|
|
const AigNode &nB = aig_indices[B];
|
|
|
|
|
|
|
|
AigNode nB_inv(nB);
|
|
|
|
nB_inv.inverter = !nB_inv.inverter;
|
|
|
|
|
|
|
|
if (nA == nB_inv)
|
|
|
|
return bool_node(inverter);
|
|
|
|
|
|
|
|
bool nA_bool = nA.portbit < 0 && nA.left_parent < 0 && nA.right_parent < 0;
|
|
|
|
bool nB_bool = nB.portbit < 0 && nB.left_parent < 0 && nB.right_parent < 0;
|
|
|
|
|
|
|
|
if (nA_bool && nB_bool) {
|
|
|
|
bool bA = nA.inverter;
|
|
|
|
bool bB = nB.inverter;
|
|
|
|
return bool_node(inverter != (bA && bB));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nA_bool) {
|
|
|
|
bool bA = nA.inverter;
|
|
|
|
if (inverter)
|
|
|
|
return bA ? not_gate(B) : bool_node(true);
|
|
|
|
return bA ? B : bool_node(false);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (nB_bool) {
|
|
|
|
bool bB = nB.inverter;
|
|
|
|
if (inverter)
|
|
|
|
return bB ? not_gate(A) : bool_node(true);
|
|
|
|
return bB ? A : bool_node(false);
|
|
|
|
}
|
2015-06-09 15:33:26 -05:00
|
|
|
|
2015-06-09 02:54:22 -05:00
|
|
|
AigNode node;
|
|
|
|
node.inverter = inverter;
|
2015-06-10 16:00:12 -05:00
|
|
|
node.left_parent = A;
|
|
|
|
node.right_parent = B;
|
|
|
|
return node2index(node);
|
|
|
|
}
|
2015-06-09 02:54:22 -05:00
|
|
|
|
2015-06-10 16:00:12 -05:00
|
|
|
int nand_gate(int A, int B)
|
|
|
|
{
|
|
|
|
return and_gate(A, B, true);
|
|
|
|
}
|
2015-06-09 02:54:22 -05:00
|
|
|
|
2015-06-10 16:00:12 -05:00
|
|
|
int or_gate(int A, int B)
|
|
|
|
{
|
|
|
|
return nand_gate(not_gate(A), not_gate(B));
|
|
|
|
}
|
|
|
|
|
|
|
|
int nor_gate(int A, int B)
|
|
|
|
{
|
|
|
|
return and_gate(not_gate(A), not_gate(B));
|
2015-06-09 02:54:22 -05:00
|
|
|
}
|
|
|
|
|
2015-06-10 16:00:12 -05:00
|
|
|
int xor_gate(int A, int B)
|
2015-06-09 15:33:26 -05:00
|
|
|
{
|
2015-06-10 16:00:12 -05:00
|
|
|
return nor_gate(and_gate(A, B), nor_gate(A, B));
|
|
|
|
}
|
|
|
|
|
|
|
|
int xnor_gate(int A, int B)
|
|
|
|
{
|
|
|
|
return or_gate(and_gate(A, B), nor_gate(A, B));
|
|
|
|
}
|
|
|
|
|
2017-05-17 02:08:29 -05:00
|
|
|
int andnot_gate(int A, int B)
|
|
|
|
{
|
|
|
|
return and_gate(A, not_gate(B));
|
|
|
|
}
|
|
|
|
|
|
|
|
int ornot_gate(int A, int B)
|
|
|
|
{
|
|
|
|
return or_gate(A, not_gate(B));
|
|
|
|
}
|
|
|
|
|
2015-06-10 16:00:12 -05:00
|
|
|
int mux_gate(int A, int B, int S)
|
|
|
|
{
|
|
|
|
return or_gate(and_gate(A, not_gate(S)), and_gate(B, S));
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
|
|
|
|
2015-06-11 03:48:16 -05:00
|
|
|
vector<int> adder(const vector<int> &A, const vector<int> &B, int carry, vector<int> *X = nullptr, vector<int> *CO = nullptr)
|
|
|
|
{
|
|
|
|
vector<int> Y(GetSize(A));
|
|
|
|
log_assert(GetSize(A) == GetSize(B));
|
|
|
|
for (int i = 0; i < GetSize(A); i++) {
|
|
|
|
Y[i] = xor_gate(xor_gate(A[i], B[i]), carry);
|
|
|
|
carry = or_gate(and_gate(A[i], B[i]), and_gate(or_gate(A[i], B[i]), carry));
|
|
|
|
if (X != nullptr)
|
|
|
|
X->at(i) = xor_gate(A[i], B[i]);
|
|
|
|
if (CO != nullptr)
|
|
|
|
CO->at(i) = carry;
|
|
|
|
}
|
|
|
|
return Y;
|
|
|
|
}
|
|
|
|
|
2015-06-09 15:33:26 -05:00
|
|
|
void outport(int node, IdString portname, int portbit = 0)
|
2015-06-09 02:54:22 -05:00
|
|
|
{
|
2015-06-09 15:33:26 -05:00
|
|
|
if (portbit < GetSize(cell->getPort(portname)))
|
|
|
|
aig->nodes.at(node).outports.push_back(pair<IdString, int>(portname, portbit));
|
2015-06-09 02:54:22 -05:00
|
|
|
}
|
2015-06-11 03:48:16 -05:00
|
|
|
|
|
|
|
void outport_bool(int node, IdString portname)
|
|
|
|
{
|
|
|
|
outport(node, portname);
|
|
|
|
for (int i = 1; i < GetSize(cell->getPort(portname)); i++)
|
|
|
|
outport(bool_node(false), portname, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
void outport_vec(const vector<int> &vec, IdString portname)
|
|
|
|
{
|
|
|
|
for (int i = 0; i < GetSize(vec); i++)
|
|
|
|
outport(vec.at(i), portname, i);
|
|
|
|
}
|
2015-06-09 02:54:22 -05:00
|
|
|
};
|
|
|
|
|
|
|
|
Aig::Aig(Cell *cell)
|
|
|
|
{
|
|
|
|
if (cell->type[0] != '$')
|
|
|
|
return;
|
|
|
|
|
2015-06-09 15:33:26 -05:00
|
|
|
AigMaker mk(this, cell);
|
2015-06-09 02:54:22 -05:00
|
|
|
name = cell->type.str();
|
|
|
|
|
2015-06-11 03:48:16 -05:00
|
|
|
string mkname_last;
|
|
|
|
bool mkname_a_signed = false;
|
|
|
|
bool mkname_b_signed = false;
|
|
|
|
bool mkname_is_signed = false;
|
|
|
|
|
2015-06-09 02:54:22 -05:00
|
|
|
cell->parameters.sort();
|
|
|
|
for (auto p : cell->parameters)
|
2015-06-11 03:48:16 -05:00
|
|
|
{
|
2020-04-02 11:51:32 -05:00
|
|
|
if (p.first == ID::A_WIDTH && mkname_a_signed) {
|
2015-06-11 03:48:16 -05:00
|
|
|
name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
|
2020-04-02 11:51:32 -05:00
|
|
|
} else if (p.first == ID::B_WIDTH && mkname_b_signed) {
|
2015-06-11 03:48:16 -05:00
|
|
|
name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
|
|
|
|
} else {
|
|
|
|
mkname_last = name;
|
|
|
|
name += stringf(":%d", p.second.as_int());
|
|
|
|
}
|
2015-06-09 02:54:22 -05:00
|
|
|
|
2015-06-11 03:48:16 -05:00
|
|
|
mkname_a_signed = false;
|
|
|
|
mkname_b_signed = false;
|
|
|
|
mkname_is_signed = false;
|
2020-04-02 11:51:32 -05:00
|
|
|
if (p.first == ID::A_SIGNED) {
|
2015-06-11 03:48:16 -05:00
|
|
|
mkname_a_signed = true;
|
|
|
|
mkname_is_signed = p.second.as_bool();
|
|
|
|
}
|
2020-04-02 11:51:32 -05:00
|
|
|
if (p.first == ID::B_SIGNED) {
|
2015-06-11 03:48:16 -05:00
|
|
|
mkname_b_signed = true;
|
|
|
|
mkname_is_signed = p.second.as_bool();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($_BUF_)))
|
2015-06-09 15:33:26 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
|
|
|
|
int A = mk.inport(ID::A, i);
|
2019-08-10 05:24:16 -05:00
|
|
|
int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A;
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport(Y, ID::Y, i);
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
2015-06-10 16:00:12 -05:00
|
|
|
goto optimize;
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
|
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
|
|
|
|
int A = mk.inport(ID::A, i);
|
|
|
|
int B = mk.inport(ID::B, i);
|
2019-08-10 05:24:16 -05:00
|
|
|
int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) :
|
|
|
|
cell->type.in(ID($_NAND_)) ? mk.nand_gate(A, B) :
|
|
|
|
cell->type.in(ID($or), ID($_OR_)) ? mk.or_gate(A, B) :
|
|
|
|
cell->type.in(ID($_NOR_)) ? mk.nor_gate(A, B) :
|
|
|
|
cell->type.in(ID($xor), ID($_XOR_)) ? mk.xor_gate(A, B) :
|
|
|
|
cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) :
|
|
|
|
cell->type.in(ID($_ANDNOT_)) ? mk.andnot_gate(A, B) :
|
|
|
|
cell->type.in(ID($_ORNOT_)) ? mk.ornot_gate(A, B) : -1;
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport(Y, ID::Y, i);
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
2015-06-10 16:00:12 -05:00
|
|
|
goto optimize;
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
|
|
|
|
2023-07-10 05:27:50 -05:00
|
|
|
if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
|
2015-06-09 15:33:26 -05:00
|
|
|
{
|
2020-04-02 11:51:32 -05:00
|
|
|
int S = mk.inport(ID::S);
|
2019-08-15 16:50:10 -05:00
|
|
|
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
|
|
|
|
int A = mk.inport(ID::A, i);
|
|
|
|
int B = mk.inport(ID::B, i);
|
2015-06-10 16:00:12 -05:00
|
|
|
int Y = mk.mux_gate(A, B, S);
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($_NMUX_))
|
2019-08-05 21:47:55 -05:00
|
|
|
Y = mk.not_gate(Y);
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport(Y, ID::Y, i);
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
2015-06-10 16:00:12 -05:00
|
|
|
goto optimize;
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)))
|
2015-06-11 03:48:16 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int Y = mk.inport(ID::A, 0);
|
|
|
|
for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) {
|
|
|
|
int A = mk.inport(ID::A, i);
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($reduce_and)) Y = mk.and_gate(A, Y);
|
|
|
|
if (cell->type == ID($reduce_or)) Y = mk.or_gate(A, Y);
|
|
|
|
if (cell->type == ID($reduce_bool)) Y = mk.or_gate(A, Y);
|
|
|
|
if (cell->type == ID($reduce_xor)) Y = mk.xor_gate(A, Y);
|
|
|
|
if (cell->type == ID($reduce_xnor)) Y = mk.xor_gate(A, Y);
|
2015-06-11 03:48:16 -05:00
|
|
|
}
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($reduce_xnor))
|
2015-06-11 03:48:16 -05:00
|
|
|
Y = mk.not_gate(Y);
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport(Y, ID::Y, 0);
|
|
|
|
for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
|
|
|
|
mk.outport(mk.bool_node(false), ID::Y, i);
|
2015-06-11 03:48:16 -05:00
|
|
|
goto optimize;
|
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or)))
|
2015-06-11 03:48:16 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int A = mk.inport(ID::A, 0), Y = -1;
|
|
|
|
for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++)
|
|
|
|
A = mk.or_gate(mk.inport(ID::A, i), A);
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type.in(ID($logic_and), ID($logic_or))) {
|
2019-08-15 16:50:10 -05:00
|
|
|
int B = mk.inport(ID::B, 0);
|
|
|
|
for (int i = 1; i < GetSize(cell->getPort(ID::B)); i++)
|
|
|
|
B = mk.or_gate(mk.inport(ID::B, i), B);
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B);
|
|
|
|
if (cell->type == ID($logic_or)) Y = mk.or_gate(A, B);
|
2015-06-11 03:48:16 -05:00
|
|
|
} else {
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($logic_not)) Y = mk.not_gate(A);
|
2015-06-11 03:48:16 -05:00
|
|
|
}
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport_bool(Y, ID::Y);
|
2015-06-11 03:48:16 -05:00
|
|
|
goto optimize;
|
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type.in(ID($add), ID($sub)))
|
2015-06-11 03:48:16 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int width = GetSize(cell->getPort(ID::Y));
|
|
|
|
vector<int> A = mk.inport_vec(ID::A, width);
|
|
|
|
vector<int> B = mk.inport_vec(ID::B, width);
|
2015-06-11 03:48:16 -05:00
|
|
|
int carry = mk.bool_node(false);
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($sub)) {
|
2015-06-11 03:48:16 -05:00
|
|
|
for (auto &n : B)
|
|
|
|
n = mk.not_gate(n);
|
|
|
|
carry = mk.not_gate(carry);
|
|
|
|
}
|
|
|
|
vector<int> Y = mk.adder(A, B, carry);
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport_vec(Y, ID::Y);
|
2015-06-11 03:48:16 -05:00
|
|
|
goto optimize;
|
|
|
|
}
|
|
|
|
|
2023-07-10 05:28:22 -05:00
|
|
|
if (cell->type.in({ID($lt), ID($gt), ID($le), ID($ge)}))
|
|
|
|
{
|
|
|
|
int width = std::max(GetSize(cell->getPort(ID::A)),
|
|
|
|
GetSize(cell->getPort(ID::B))) + 1;
|
|
|
|
vector<int> A = mk.inport_vec(ID::A, width);
|
|
|
|
vector<int> B = mk.inport_vec(ID::B, width);
|
|
|
|
|
|
|
|
if (cell->type.in({ID($gt), ID($ge)}))
|
|
|
|
std::swap(A, B);
|
|
|
|
|
|
|
|
int carry = mk.bool_node(!cell->type.in({ID($le), ID($ge)}));
|
|
|
|
for (auto &n : B)
|
|
|
|
n = mk.not_gate(n);
|
|
|
|
vector<int> Y = mk.adder(A, B, carry);
|
|
|
|
mk.outport(Y.back(), ID::Y);
|
|
|
|
for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
|
|
|
|
mk.outport(mk.bool_node(false), ID::Y, i);
|
|
|
|
goto optimize;
|
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($alu))
|
2015-06-11 03:48:16 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int width = GetSize(cell->getPort(ID::Y));
|
|
|
|
vector<int> A = mk.inport_vec(ID::A, width);
|
|
|
|
vector<int> B = mk.inport_vec(ID::B, width);
|
2020-04-02 11:51:32 -05:00
|
|
|
int carry = mk.inport(ID::CI);
|
|
|
|
int binv = mk.inport(ID::BI);
|
2015-06-11 03:48:16 -05:00
|
|
|
for (auto &n : B)
|
|
|
|
n = mk.xor_gate(n, binv);
|
|
|
|
vector<int> X(width), CO(width);
|
|
|
|
vector<int> Y = mk.adder(A, B, carry, &X, &CO);
|
|
|
|
for (int i = 0; i < width; i++)
|
|
|
|
X[i] = mk.xor_gate(A[i], B[i]);
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport_vec(Y, ID::Y);
|
2020-04-02 11:51:32 -05:00
|
|
|
mk.outport_vec(X, ID::X);
|
|
|
|
mk.outport_vec(CO, ID::CO);
|
2015-06-11 03:48:16 -05:00
|
|
|
goto optimize;
|
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type.in(ID($eq), ID($ne)))
|
2015-06-11 03:48:16 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
|
|
|
|
vector<int> A = mk.inport_vec(ID::A, width);
|
|
|
|
vector<int> B = mk.inport_vec(ID::B, width);
|
2015-06-11 03:48:16 -05:00
|
|
|
int Y = mk.bool_node(false);
|
|
|
|
for (int i = 0; i < width; i++)
|
|
|
|
Y = mk.or_gate(Y, mk.xor_gate(A[i], B[i]));
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($eq))
|
2015-06-11 03:48:16 -05:00
|
|
|
Y = mk.not_gate(Y);
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport_bool(Y, ID::Y);
|
2015-06-11 03:48:16 -05:00
|
|
|
goto optimize;
|
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($_AOI3_))
|
2015-06-09 15:33:26 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int A = mk.inport(ID::A);
|
|
|
|
int B = mk.inport(ID::B);
|
2020-04-02 11:51:32 -05:00
|
|
|
int C = mk.inport(ID::C);
|
2015-06-10 16:00:12 -05:00
|
|
|
int Y = mk.nor_gate(mk.and_gate(A, B), C);
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport(Y, ID::Y);
|
2015-06-10 16:00:12 -05:00
|
|
|
goto optimize;
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($_OAI3_))
|
2015-06-09 15:33:26 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int A = mk.inport(ID::A);
|
|
|
|
int B = mk.inport(ID::B);
|
2020-04-02 11:51:32 -05:00
|
|
|
int C = mk.inport(ID::C);
|
2015-06-10 16:00:12 -05:00
|
|
|
int Y = mk.nand_gate(mk.or_gate(A, B), C);
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport(Y, ID::Y);
|
2015-06-10 16:00:12 -05:00
|
|
|
goto optimize;
|
2015-06-09 15:33:26 -05:00
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($_AOI4_))
|
2015-06-09 02:54:22 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int A = mk.inport(ID::A);
|
|
|
|
int B = mk.inport(ID::B);
|
2020-04-02 11:51:32 -05:00
|
|
|
int C = mk.inport(ID::C);
|
|
|
|
int D = mk.inport(ID::D);
|
2015-06-10 16:00:12 -05:00
|
|
|
int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D));
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport(Y, ID::Y);
|
2015-06-10 16:00:12 -05:00
|
|
|
goto optimize;
|
2015-06-09 02:54:22 -05:00
|
|
|
}
|
|
|
|
|
2019-08-10 05:24:16 -05:00
|
|
|
if (cell->type == ID($_OAI4_))
|
2015-06-09 02:54:22 -05:00
|
|
|
{
|
2019-08-15 16:50:10 -05:00
|
|
|
int A = mk.inport(ID::A);
|
|
|
|
int B = mk.inport(ID::B);
|
2020-04-02 11:51:32 -05:00
|
|
|
int C = mk.inport(ID::C);
|
|
|
|
int D = mk.inport(ID::D);
|
2019-04-23 11:54:00 -05:00
|
|
|
int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
|
2019-08-15 16:50:10 -05:00
|
|
|
mk.outport(Y, ID::Y);
|
2015-06-10 16:00:12 -05:00
|
|
|
goto optimize;
|
2015-06-09 02:54:22 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
name.clear();
|
2015-06-10 16:00:12 -05:00
|
|
|
return;
|
|
|
|
|
|
|
|
optimize:;
|
|
|
|
pool<int> used_old_ids;
|
|
|
|
vector<AigNode> new_nodes;
|
|
|
|
dict<int, int> old_to_new_ids;
|
|
|
|
old_to_new_ids[-1] = -1;
|
|
|
|
|
|
|
|
for (int i = GetSize(nodes)-1; i >= 0; i--) {
|
|
|
|
if (!nodes[i].outports.empty())
|
|
|
|
used_old_ids.insert(i);
|
|
|
|
if (!used_old_ids.count(i))
|
|
|
|
continue;
|
|
|
|
if (nodes[i].left_parent >= 0)
|
|
|
|
used_old_ids.insert(nodes[i].left_parent);
|
|
|
|
if (nodes[i].right_parent >= 0)
|
|
|
|
used_old_ids.insert(nodes[i].right_parent);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (int i = 0; i < GetSize(nodes); i++) {
|
|
|
|
if (!used_old_ids.count(i))
|
|
|
|
continue;
|
|
|
|
nodes[i].left_parent = old_to_new_ids.at(nodes[i].left_parent);
|
|
|
|
nodes[i].right_parent = old_to_new_ids.at(nodes[i].right_parent);
|
|
|
|
old_to_new_ids[i] = GetSize(new_nodes);
|
|
|
|
new_nodes.push_back(nodes[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
new_nodes.swap(nodes);
|
2015-06-09 02:54:22 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
YOSYS_NAMESPACE_END
|