yosys/CHANGELOG

List of major changes and improvements between releases
=======================================================


Yosys 0.4 .. Yosys 0.4+
-----------------------

 ... TBD ...


Yosys 0.3.0 .. Yosys 0.4
------------------------

 * Platform Support
     - Added support for mxe-based cross-builds for win32
     - Added sourcecode-export as VisualStudio project
     - Added experimental EMCC (JavaScript) support

 * Verilog Frontend
     - Added -sv option for SystemVerilog (and automatic *.sv file support)
     - Added support for real-valued constants and constant expressions
     - Added support for non-standard "via_celltype" attribute on task/func
     - Added support for non-standard "module mod_name(...);" syntax
     - Added support for non-standard """ macro bodies
     - Added support for array with more than one dimension
     - Added support for $readmemh and $readmemb
     - Added support for DPI functions

 * Changes in internal cell library
     - Added $shift and $shiftx cell types
     - Added $alu, $lcu, $fa and $macc cell types
     - Removed $bu0 and $safe_pmux cell types
     - $mem/$memwr WR_EN input is now a per-data-bit enable signal
     - Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
     - Renamed ports of $lut cells (from I->O to A->Y)
     - Renamed $_INV_ to $_NOT_

 * Changes for simple synthesis flows
     - There is now a "synth" command with a recommended default script
     - Many improvements in synthesis of arithmetic functions to gates
	 - Multiplieres and adders with many operands are using carry-save adder trees
         - Remaining adders are now implemented using Brent–Kung carry look-ahead adders
     - Various new high-level optimizations on RTL netlist
     - Various improvements in FSM optimization
     - Updated ABC to hg 5b5af75f1dda (from 2014-11-07)

 * Changes in internal APIs and RTLIL
     - Added log_id() and log_cell() helper functions
     - Added function-like cell creation helpers
     - Added GetSize() function (like .size() but with int)
     - Major refactoring of RTLIL::Module and related classes
     - Major refactoring of RTLIL::SigSpec and related classes
     - Now RTLIL::IdString is essentially an int
     - Added macros for code coverage counters
     - Added some Makefile magic for pretty make logs
     - Added "kernel/yosys.h" with all the core definitions
     - Chanded a lot of code from FILE* to c++ streams
     - Added RTLIL::Monitor API and "trace" command
     - Added "Yosys" C++ namespace

 * Changes relevant to SAT solving
     - Added ezSAT::keep_cnf() and ezSAT::non_incremental()
     - Added native ezSAT support for vector shift ops
     - Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)

 * New commands (or large improvements to commands)
     - Added "synth" command with default script
     - Added "share" (finally some real resource sharing)
     - Added "memory_share" (reduce number of ports on memories)
     - Added "wreduce" and "alumacc" commands
     - Added "opt -keepdc -fine -full -fast"
     - Added some "test_*" commands

 * Various other changes
     - Added %D and %c select operators
     - Added support for labels in yosys scripts
     - Added support for here-documents in yosys scripts
     - Support "+/" prefix for files from proc_share_dir
     - Added "autoidx" statement to ilang language
     - Switched from "yosys-svgviewer" to "xdot"
     - Renamed "stdcells.v" to "techmap.v"
     - Various bug fixes and small improvements
     - Improved welcome and bye messages


Yosys 0.2.0 .. Yosys 0.3.0
--------------------------

 * Driver program and overall behavior:
     - Added "design -push" and "design -pop"
     - Added "tee" command for redirecting log output

 * Changes in the internal cell library:
     - Added $dlatchsr and $_DLATCHSR_???_ cell types

 * Improvements in Verilog frontend:
     - Improved support for const functions (case, always, repeat)
     - The generate..endgenerate keywords are now optional
     - Added support for arrays of module instances
     - Added support for "`default_nettype" directive
     - Added support for "`line" directive

 * Other front- and back-ends:
     - Various changes to "write_blif" options
     - Various improvements in EDIF backend
     - Added "vhdl2verilog" pseudo-front-end
     - Added "verific" pseudo-front-end

 * Improvements in technology mapping:
     - Added support for recursive techmap
     - Added CONSTMSK and CONSTVAL features to techmap
     - Added _TECHMAP_CONNMAP_*_ feature to techmap
     - Added _TECHMAP_REPLACE_ feature to techmap
     - Added "connwrappers" command for wrap-extract-unwrap method
     - Added "extract -map %<design_name>" feature
     - Added "extract -ignore_param ..." and "extract -ignore_parameters"
     - Added "techmap -max_iter" option

 * Improvements to "eval" and "sat" framework:
     - Now include a copy of Minisat (with build fixes applied)
     - Switched to Minisat::SimpSolver as SAT back-end
     - Added "sat -dump_vcd" feature
     - Added "sat -dump_cnf" feature
     - Added "sat -initsteps <N>" feature
     - Added "freduce -stop <N>" feature
     - Added "fredure -dump <prefix>" feature

 * Integration with ABC:
     - Updated ABC rev to 7600ffb9340c

 * Improvements in the internal APIs:
     - Added RTLIL::Module::add... helper methods
     - Various build fixes for OSX (Darwin) and OpenBSD


Yosys 0.1.0 .. Yosys 0.2.0
--------------------------

 * Changes to the driver program:
     - Added "yosys -h" and "yosys -H"
     - Added support for backslash line continuation in scripts
     - Added support for #-comments in same line as command
     - Added "echo" and "log" commands

 * Improvements in Verilog frontend:
     - Added support for local registers in named blocks
     - Added support for "case" in "generate" blocks
     - Added support for $clog2 system function
     - Added support for basic SystemVerilog assert statements
     - Added preprocessor support for macro arguments
     - Added preprocessor support for `elsif statement
     - Added "verilog_defaults" command
     - Added read_verilog -icells option
     - Added support for constant sizes from parameters
     - Added "read_verilog -setattr"
     - Added support for function returning 'integer'
     - Added limited support for function calls in parameter values
     - Added "read_verilog -defer" to suppress evaluation of modules with default parameters

 * Other front- and back-ends:
     - Added BTOR backend
     - Added Liberty frontend

 * Improvements in technology mapping:
     - The "dfflibmap" command now strongly prefers solutions with
           no inverters in clock paths
     - The "dfflibmap" command now prefers cells with smaller area
     - Added support for multiple -map options to techmap
     - Added "dfflibmap" support for //-comments in liberty files
     - Added "memory_unpack" command to revert "memory_collect"
     - Added standard techmap rule "techmap -share_map pmux2mux.v"
     - Added "iopadmap -bits"
     - Added "setundef" command
     - Added "hilomap" command

 * Changes in the internal cell library:
     - Major rewrite of simlib.v for better compatibility with other tools
     - Added PRIORITY parameter to $memwr cells
     - Added TRANSPARENT parameter to $memrd cells
     - Added RD_TRANSPARENT parameter to $mem cells
     - Added $bu0 cell (always 0-extend, even undef MSB)
     - Added $assert cell type
     - Added $slice and $concat cell types

 * Integration with ABC:
     - Updated ABC to hg rev 2058c8ccea68
     - Tighter integration of ABC build with Yosys build. The make
           targets 'make abc' and 'make install-abc' are now obsolete.
     - Added support for passing FFs from one clock domain through ABC
     - Now always use BLIF as exchange format with ABC
     - Added support for "abc -script +<command_sequence>"
     - Improved standard ABC recipe
     - Added support for "keep" attribute to abc command
     - Added "abc -dff / -clk / -keepff" options

 * Improvements to "eval" and "sat" framework:
     - Added support for "0" and "~0" in right-hand side -set expressions
     - Added "eval -set-undef" and "eval -table"
     - Added "sat -set-init" and "sat -set-init-*" for sequential problems
     - Added undef support to SAT solver, incl. various new "sat" options
     - Added correct support for === and !== for "eval" and "sat"
     - Added "sat -tempinduct" (default -seq is now non-induction sequential)
     - Added "sat -prove-asserts"
     - Complete rewrite of the 'freduce' command
     - Added "miter" command
     - Added "sat -show-inputs" and "sat -show-outputs"
     - Added "sat -ignore_unknown_cells" (now produce an error by default)
     - Added "sat -falsify"
     - Now "sat -verify" and "sat -falsify" can also be used without "-prove"
     - Added "expose" command
     - Added support for @<sel_name> to sat and eval signal expressions

 * Changes in the 'make test' framework and auxilary test tools:
     - Added autotest.sh -p and -f options
     - Replaced autotest.sh ISIM support with XSIM support
     - Added test cases for SAT framework

 * Added "abbreviated IDs":
     - Now $<something>$foo can be abbriviated as $foo.
     - Usually this last part is a unique id (from RTLIL::autoidx)
     - This abbreviated IDs are now also used in "show" output

 * Other changes to selection framework:
     - Now */ is optional in */<mode>:<arg> expressions
     - Added "select -assert-none" and "select -assert-any"
     - Added support for matching modules by attribute (A:<expr>)
     - Added "select -none"
     - Added support for r:<expr> pattern for matching cell parameters
     - Added support for !=, <, <=, >=, > for attribute and parameter matching
     - Added support for %s for selecting sub-modules
     - Added support for %m for expanding selections to whole modules
     - Added support for i:*, o:* and x:* pattern for selecting module ports
     - Added support for s:<expr> pattern for matching wire width
     - Added support for %a operation to select wire aliases

 * Various other changes to commands and options:
     - The "ls" command now supports wildcards
     - Added "show -pause" and "show -format dot"
     - Added "show -color" support for cells
     - Added "show -label" and "show -notitle"
     - Added "dump -m" and "dump -n"
     - Added "history" command
     - Added "rename -hide"
     - Added "connect" command
     - Added "splitnets -driver"
     - Added "opt_const -mux_undef"
     - Added "opt_const -mux_bool"
     - Added "opt_const -undriven"
     - Added "opt -mux_undef -mux_bool -undriven -purge"
     - Added "hierarchy -libdir"
     - Added "hierarchy -purge_lib" (by default now do not remove lib cells)
     - Added "delete" command
     - Added "dump -append"
     - Added "setattr" and "setparam" commands
     - Added "design -stash/-copy-from/-copy-to"
     - Added "copy" command
     - Added "splice" command