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Tagging Yosys 0.3.0
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CHANGELOG
48
CHANGELOG
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@ -3,10 +3,54 @@ List of changes and major improvements between releases
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=======================================================
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Yosys 0.2.0 .. Yoys 0.2.0+
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Yosys 0.2.0 .. Yoys 0.3.0
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--------------------------
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... TBD ...
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* Driver program and overall behavior:
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- Added "design -push" and "design -pop"
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- Added "tee" command for redirecting log output
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* Changes in the internal cell library:
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- Added $dlatchsr and $_DLATCHSR_???_ cell types
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* Improvements in Verilog frontend:
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- Improved support for const functions (case, always, repeat)
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- The generate..endgenerate keywords are now optional
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- Added support for arrays of module instances
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- Added support for "`default_nettype" directive
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- Added support for "`line" directive
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* Other front- and back-ends:
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- Various changes to "write_blif" options
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- Various improvements in EDIF backend
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- Added "vhdl2verilog" pseudo-front-end
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- Added "verific" pseudo-front-end
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* Improvements in technology mapping:
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- Added support for recursive techmap
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- Added CONSTMSK and CONSTVAL features to techmap
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- Added _TECHMAP_CONNMAP_*_ feature to techmap
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- Added _TECHMAP_REPLACE_ feature to techmap
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- Added "connwrappers" command for wrap-extract-unwrap method
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- Added "extract -map %<design_name>" feature
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- Added "extract -ignore_param ..." and "extract -ignore_parameters"
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- Added "techmap -max_iter" option
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* Improvements to "eval" and "sat" framework:
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- Now include a copy of Minisat (with build fixes applied)
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- Switched to Minisat::SimpSolver as SAT back-end
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- Added "sat -dump_vcd" feature
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- Added "sat -dump_cnf" feature
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- Added "sat -initsteps <N>" feature
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- Added "freduce -stop <N>" feature
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- Added "fredure -dump <prefix>" feature
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* Integration with ABC:
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- Updated ABC rev to 7600ffb9340c
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* Improvements in the internal APIs:
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- Added RTLIL::Module::add... helper methods
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- Various build fixes for OSX (Darwin) and OpenBSD
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Yosys 0.1.0 .. Yoys 0.2.0
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