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yosys/techlibs/anlogic/drams.txt

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anlogic: add support for Eagle Distributed RAM The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-14 02:50:37 -06:00
bram $__ANLOGIC_DRAM16X4
init 0
abits 4
anlogic: fix dbits of Anlogic Eagle DRAM16X4 The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM bits. Fix the dbits number in the RAM configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-18 00:38:44 -06:00
dbits 4
anlogic: add support for Eagle Distributed RAM The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-12-14 02:50:37 -06:00
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 1
endbram
match $__ANLOGIC_DRAM16X4
make_outreg
endmatch