mirror of https://github.com/YosysHQ/yosys.git
62 lines
997 B
Verilog
62 lines
997 B
Verilog
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module \$__mul_wrapper (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [17:0] A;
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input [24:0] B;
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output [47:0] Y;
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wire [A_WIDTH-1:0] A_ORIG = A;
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wire [B_WIDTH-1:0] B_ORIG = B;
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wire [Y_WIDTH-1:0] Y_ORIG;
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assign Y = Y_ORIG;
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\$mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_ORIG),
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.B(B_ORIG),
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.Y(Y_ORIG)
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);
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endmodule
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module \$__add_wrapper (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [47:0] A;
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input [47:0] B;
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output [47:0] Y;
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wire [A_WIDTH-1:0] A_ORIG = A;
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wire [B_WIDTH-1:0] B_ORIG = B;
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wire [Y_WIDTH-1:0] Y_ORIG;
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assign Y = Y_ORIG;
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\$add #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) _TECHMAP_REPLACE_ (
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.A(A_ORIG),
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.B(B_ORIG),
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.Y(Y_ORIG)
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);
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endmodule
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