Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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2019-08-12 19:35:54 -05:00
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* Copyright (C) 2019 Marcin Kościelnicki <mwk@0x04.net>
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void split_portname_pair(std::string &port1, std::string &port2)
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{
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size_t pos = port1.find_first_of(':');
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if (pos != std::string::npos) {
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port2 = port1.substr(pos+1);
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port1 = port1.substr(0, pos);
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}
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}
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struct ClkbufmapPass : public Pass {
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ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
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2020-06-18 18:34:52 -05:00
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void help() override
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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{
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2019-08-23 13:14:42 -05:00
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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log("\n");
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log(" clkbufmap [options] [selection]\n");
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log("\n");
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2019-08-23 13:14:42 -05:00
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log("Inserts global buffers between nets connected to clock inputs and their drivers.\n");
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log("\n");
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log("In the absence of any selection, all wires without the 'clkbuf_inhibit'\n");
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log("attribute will be considered for global buffer insertion.\n");
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log("Alternatively, to consider all wires without the 'buffer_type' attribute set to\n");
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log("'none' or 'bufr' one would specify:\n");
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log(" 'w:* a:buffer_type=none a:buffer_type=bufr %%u %%d'\n");
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log("as the selection.\n");
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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log("\n");
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log(" -buf <celltype> <portname_out>:<portname_in>\n");
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log(" Specifies the cell type to use for the global buffers\n");
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log(" and its port names. The first port will be connected to\n");
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log(" the clock network sinks, and the second will be connected\n");
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log(" to the actual clock source. This option is required.\n");
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log("\n");
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log(" -inpad <celltype> <portname_out>:<portname_in>\n");
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log(" If specified, a PAD cell of the given type is inserted on\n");
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log(" clock nets that are also top module's inputs (in addition\n");
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log(" to the global buffer).\n");
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log("\n");
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}
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void module_queue(Design *design, Module *module, std::vector<Module *> &modules_sorted, pool<Module *> &modules_processed) {
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if (modules_processed.count(module))
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return;
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for (auto cell : module->cells()) {
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Module *submodule = design->module(cell->type);
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if (!submodule)
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continue;
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module_queue(design, submodule, modules_sorted, modules_processed);
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}
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modules_sorted.push_back(module);
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modules_processed.insert(module);
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}
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2020-06-18 18:34:52 -05:00
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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{
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log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n");
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std::string buf_celltype, buf_portname, buf_portname2;
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std::string inpad_celltype, inpad_portname, inpad_portname2;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-buf" && argidx+2 < args.size()) {
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buf_celltype = args[++argidx];
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buf_portname = args[++argidx];
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split_portname_pair(buf_portname, buf_portname2);
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continue;
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}
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if (arg == "-inpad" && argidx+2 < args.size()) {
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inpad_celltype = args[++argidx];
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inpad_portname = args[++argidx];
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split_portname_pair(inpad_portname, inpad_portname2);
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continue;
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}
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break;
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}
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2019-08-23 13:14:42 -05:00
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bool select = false;
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if (argidx < args.size()) {
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if (args[argidx].compare(0, 1, "-") != 0)
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select = true;
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extra_args(args, argidx, design);
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}
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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if (buf_celltype.empty())
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2019-08-23 13:14:42 -05:00
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log_error("The -buf option is required.\n");
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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// Cell type, port name, bit index.
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pool<pair<IdString, pair<IdString, int>>> sink_ports;
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pool<pair<IdString, pair<IdString, int>>> buf_ports;
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2019-11-24 09:05:45 -06:00
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dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out;
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dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in;
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Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
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// Process submodules before module using them.
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std::vector<Module *> modules_sorted;
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pool<Module *> modules_processed;
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for (auto module : design->selected_modules())
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module_queue(design, module, modules_sorted, modules_processed);
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for (auto module : modules_sorted)
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{
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if (module->get_blackbox_attribute()) {
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2019-08-23 12:03:41 -05:00
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for (auto port : module->ports) {
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auto wire = module->wire(port);
|
2020-04-02 11:51:32 -05:00
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if (wire->get_bool_attribute(ID::clkbuf_driver))
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
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|
for (int i = 0; i < GetSize(wire); i++)
|
2019-08-13 14:36:59 -05:00
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|
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
|
2020-04-02 11:51:32 -05:00
|
|
|
if (wire->get_bool_attribute(ID::clkbuf_sink))
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
|
|
for (int i = 0; i < GetSize(wire); i++)
|
2019-08-13 14:36:59 -05:00
|
|
|
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
|
2020-04-02 11:51:32 -05:00
|
|
|
auto it = wire->attributes.find(ID::clkbuf_inv);
|
2019-11-24 09:05:45 -06:00
|
|
|
if (it != wire->attributes.end()) {
|
|
|
|
IdString in_name = RTLIL::escape_id(it->second.decode_string());
|
|
|
|
for (int i = 0; i < GetSize(wire); i++) {
|
|
|
|
inv_ports_out[make_pair(module->name, make_pair(wire->name, i))] = make_pair(in_name, i);
|
|
|
|
inv_ports_in[make_pair(module->name, make_pair(in_name, i))] = make_pair(wire->name, i);
|
|
|
|
}
|
|
|
|
}
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
|
|
}
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
pool<SigBit> sink_wire_bits;
|
|
|
|
pool<SigBit> buf_wire_bits;
|
|
|
|
pool<SigBit> driven_wire_bits;
|
|
|
|
SigMap sigmap(module);
|
|
|
|
// bit -> (buffer, buffer's input)
|
|
|
|
dict<SigBit, pair<Cell *, Wire *>> buffered_bits;
|
|
|
|
|
|
|
|
// First, collect nets that could use a clock buffer.
|
|
|
|
for (auto cell : module->cells())
|
|
|
|
for (auto port : cell->connections())
|
|
|
|
for (int i = 0; i < port.second.size(); i++)
|
|
|
|
if (sink_ports.count(make_pair(cell->type, make_pair(port.first, i))))
|
|
|
|
sink_wire_bits.insert(sigmap(port.second[i]));
|
|
|
|
|
|
|
|
// Second, collect ones that already have a clock buffer.
|
|
|
|
for (auto cell : module->cells())
|
|
|
|
for (auto port : cell->connections())
|
|
|
|
for (int i = 0; i < port.second.size(); i++)
|
|
|
|
if (buf_ports.count(make_pair(cell->type, make_pair(port.first, i))))
|
|
|
|
buf_wire_bits.insert(sigmap(port.second[i]));
|
|
|
|
|
2019-11-24 09:05:45 -06:00
|
|
|
// Third, propagate tags through inverters.
|
|
|
|
bool retry = true;
|
|
|
|
while (retry) {
|
|
|
|
retry = false;
|
|
|
|
for (auto cell : module->cells())
|
|
|
|
for (auto port : cell->connections())
|
|
|
|
for (int i = 0; i < port.second.size(); i++) {
|
|
|
|
auto it = inv_ports_out.find(make_pair(cell->type, make_pair(port.first, i)));
|
|
|
|
auto bit = sigmap(port.second[i]);
|
|
|
|
// If output of an inverter is connected to a sink, mark it as buffered,
|
|
|
|
// and request a buffer on the inverter's input instead.
|
|
|
|
if (it != inv_ports_out.end() && !buf_wire_bits.count(bit) && sink_wire_bits.count(bit)) {
|
|
|
|
buf_wire_bits.insert(bit);
|
|
|
|
auto other_bit = sigmap(cell->getPort(it->second.first)[it->second.second]);
|
|
|
|
sink_wire_bits.insert(other_bit);
|
|
|
|
retry = true;
|
|
|
|
}
|
|
|
|
// If input of an inverter is marked as already-buffered,
|
|
|
|
// mark its output already-buffered as well.
|
|
|
|
auto it2 = inv_ports_in.find(make_pair(cell->type, make_pair(port.first, i)));
|
|
|
|
if (it2 != inv_ports_in.end() && buf_wire_bits.count(bit)) {
|
|
|
|
auto other_bit = sigmap(cell->getPort(it2->second.first)[it2->second.second]);
|
|
|
|
if (!buf_wire_bits.count(other_bit)) {
|
|
|
|
buf_wire_bits.insert(other_bit);
|
|
|
|
retry = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
|
|
// Collect all driven bits.
|
|
|
|
for (auto cell : module->cells())
|
|
|
|
for (auto port : cell->connections())
|
|
|
|
if (cell->output(port.first))
|
|
|
|
for (int i = 0; i < port.second.size(); i++)
|
|
|
|
driven_wire_bits.insert(port.second[i]);
|
|
|
|
|
|
|
|
// Insert buffers.
|
|
|
|
std::vector<pair<Wire *, Wire *>> input_queue;
|
2019-08-27 10:26:47 -05:00
|
|
|
// Copy current wire list, as we will be adding new ones during iteration.
|
|
|
|
std::vector<Wire *> wires(module->wires());
|
|
|
|
for (auto wire : wires)
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
|
|
{
|
|
|
|
// Should not happen.
|
|
|
|
if (wire->port_input && wire->port_output)
|
|
|
|
continue;
|
2019-08-27 10:26:47 -05:00
|
|
|
bool process_wire = module->selected(wire);
|
2020-04-02 11:51:32 -05:00
|
|
|
if (!select && wire->get_bool_attribute(ID::clkbuf_inhibit))
|
2019-08-27 10:26:47 -05:00
|
|
|
process_wire = false;
|
|
|
|
if (!process_wire) {
|
|
|
|
// This wire is supposed to be bypassed, so make sure we don't buffer it in
|
|
|
|
// some buffer higher up in the hierarchy.
|
|
|
|
if (wire->port_output)
|
|
|
|
for (int i = 0; i < GetSize(wire); i++)
|
|
|
|
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
|
|
continue;
|
2019-08-27 10:26:47 -05:00
|
|
|
}
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
|
|
|
|
|
|
pool<int> input_bits;
|
|
|
|
|
|
|
|
for (int i = 0; i < GetSize(wire); i++)
|
|
|
|
{
|
|
|
|
SigBit wire_bit(wire, i);
|
|
|
|
SigBit mapped_wire_bit = sigmap(wire_bit);
|
|
|
|
if (buf_wire_bits.count(mapped_wire_bit)) {
|
|
|
|
// Already buffered downstream. If this is an output, mark it.
|
|
|
|
if (wire->port_output)
|
|
|
|
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
|
|
|
|
} else if (!sink_wire_bits.count(mapped_wire_bit)) {
|
|
|
|
// Nothing to do.
|
2020-03-12 14:57:01 -05:00
|
|
|
} else if (driven_wire_bits.count(wire_bit) || (wire->port_input && module->get_bool_attribute(ID::top))) {
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
|
|
// Clock network not yet buffered, driven by one of
|
|
|
|
// our cells or a top-level input -- buffer it.
|
|
|
|
|
|
|
|
log("Inserting %s on %s.%s[%d].\n", buf_celltype.c_str(), log_id(module), log_id(wire), i);
|
|
|
|
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
|
|
|
|
Wire *iwire = module->addWire(NEW_ID);
|
|
|
|
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
|
|
|
|
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
|
2020-03-12 14:57:01 -05:00
|
|
|
if (wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top)) {
|
Add clock buffer insertion pass, improve iopadmap.
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-12 10:57:43 -05:00
|
|
|
log("Inserting %s on %s.%s[%d].\n", inpad_celltype.c_str(), log_id(module), log_id(wire), i);
|
|
|
|
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
|
|
|
|
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
|
|
|
|
iwire = module->addWire(NEW_ID);
|
|
|
|
cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
|
|
|
|
}
|
|
|
|
buffered_bits[mapped_wire_bit] = make_pair(cell, iwire);
|
|
|
|
|
|
|
|
if (wire->port_input) {
|
|
|
|
input_bits.insert(i);
|
|
|
|
}
|
|
|
|
} else if (wire->port_input) {
|
|
|
|
// A clock input in a submodule -- mark it, let higher level
|
|
|
|
// worry about it.
|
|
|
|
if (wire->port_input)
|
|
|
|
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!input_bits.empty()) {
|
|
|
|
// This is an input port and some buffers were inserted -- we need
|
|
|
|
// to create a new input wire and transfer attributes.
|
|
|
|
Wire *new_wire = module->addWire(NEW_ID, wire);
|
|
|
|
|
|
|
|
for (int i = 0; i < wire->width; i++) {
|
|
|
|
SigBit wire_bit(wire, i);
|
|
|
|
SigBit mapped_wire_bit = sigmap(wire_bit);
|
|
|
|
auto it = buffered_bits.find(mapped_wire_bit);
|
|
|
|
if (it != buffered_bits.end()) {
|
|
|
|
|
|
|
|
module->connect(it->second.second, SigSpec(new_wire, i));
|
|
|
|
} else {
|
|
|
|
module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
input_queue.push_back(make_pair(wire, new_wire));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Mark any newly-buffered output ports as such.
|
|
|
|
for (auto wire : module->selected_wires()) {
|
|
|
|
if (wire->port_input || !wire->port_output)
|
|
|
|
continue;
|
|
|
|
for (int i = 0; i < GetSize(wire); i++)
|
|
|
|
{
|
|
|
|
SigBit wire_bit(wire, i);
|
|
|
|
SigBit mapped_wire_bit = sigmap(wire_bit);
|
|
|
|
if (buffered_bits.count(mapped_wire_bit))
|
|
|
|
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Reconnect the drivers to buffer inputs.
|
|
|
|
for (auto cell : module->cells())
|
|
|
|
for (auto port : cell->connections()) {
|
|
|
|
if (!cell->output(port.first))
|
|
|
|
continue;
|
|
|
|
SigSpec sig = port.second;
|
|
|
|
bool newsig = false;
|
|
|
|
for (auto &bit : sig) {
|
|
|
|
const auto it = buffered_bits.find(sigmap(bit));
|
|
|
|
if (it == buffered_bits.end())
|
|
|
|
continue;
|
|
|
|
// Avoid substituting buffer's own output pin.
|
|
|
|
if (cell == it->second.first)
|
|
|
|
continue;
|
|
|
|
bit = it->second.second;
|
|
|
|
newsig = true;
|
|
|
|
}
|
|
|
|
if (newsig)
|
|
|
|
cell->setPort(port.first, sig);
|
|
|
|
}
|
|
|
|
|
|
|
|
// This has to be done last, to avoid upsetting sigmap before the port reconnections.
|
|
|
|
for (auto &it : input_queue) {
|
|
|
|
Wire *wire = it.first;
|
|
|
|
Wire *new_wire = it.second;
|
|
|
|
module->swap_names(new_wire, wire);
|
|
|
|
wire->attributes.clear();
|
|
|
|
wire->port_id = 0;
|
|
|
|
wire->port_input = false;
|
|
|
|
wire->port_output = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
module->fixup_ports();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} ClkbufmapPass;
|
|
|
|
|
|
|
|
PRIVATE_NAMESPACE_END
|