mirror of https://github.com/YosysHQ/yosys.git
14 lines
497 B
Plaintext
14 lines
497 B
Plaintext
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read_verilog fsm.v
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hierarchy -top top
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proc
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flatten
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equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:SB_DFFESR
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select -assert-count 2 t:SB_DFFSR
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select -assert-count 1 t:SB_DFFSS
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select -assert-count 13 t:SB_LUT4
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select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D
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