mirror of https://github.com/YosysHQ/yosys.git
14 lines
497 B
Plaintext
14 lines
497 B
Plaintext
read_verilog fsm.v
|
|
hierarchy -top top
|
|
proc
|
|
flatten
|
|
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 2 t:SB_DFFESR
|
|
select -assert-count 2 t:SB_DFFSR
|
|
select -assert-count 1 t:SB_DFFSS
|
|
select -assert-count 13 t:SB_LUT4
|
|
select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D
|