yosys/techlibs/ice40/tests/test_arith.ys

read_verilog test_arith.v
synth_ice40
techmap -map ../cells_sim.v
rename test gate

read_verilog test_arith.v
rename test gold

miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
Added ice40 test_arith 2015-04-18 02:33:34 -05:00			`read_verilog test_arith.v`
			`synth_ice40`
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 11:14:48 -05:00			`techmap -map ../cells_sim.v`
Added ice40 test_arith 2015-04-18 02:33:34 -05:00			`rename test gate`

			`read_verilog test_arith.v`
			`rename test gold`

			`miter -equiv -flatten -make_outputs gold gate miter`
			`sat -verify -prove trigger 0 -show-ports miter`