yosys/tests/arch/xilinx/mux_lut4.ys

read_verilog ../common/mux.v
design -save read

hierarchy -top mux2
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3

select -assert-none t:LUT3 %% t:* %D


design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 4 t:LUT1
select -assert-count 2 t:MUXF5
select -assert-count 1 t:MUXF6

select -assert-none t:LUT1 t:MUXF5 t:MUXF6 %% t:* %D


design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-max 5 t:LUT1
select -assert-max 3 t:LUT3
select -assert-max 3 t:LUT4
select -assert-max 3 t:MUXF5
select -assert-count 1 t:MUXF6

select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D


design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-max 32 t:LUT*
select -assert-max 8 t:MUXF6
select -assert-max 4 t:MUXF7

select -assert-none t:LUT* t:MUXF5 t:MUXF6 t:MUXF7 %% t:* %D