2019-07-17 16:25:40 -05:00
|
|
|
module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y);
|
2019-07-15 16:18:44 -05:00
|
|
|
wire [47:0] P_48;
|
|
|
|
DSP48E1 #(
|
|
|
|
// Disable all registers
|
|
|
|
.ACASCREG(0),
|
|
|
|
.ADREG(0),
|
|
|
|
.A_INPUT("DIRECT"),
|
|
|
|
.ALUMODEREG(0),
|
|
|
|
.AREG(0),
|
|
|
|
.BCASCREG(0),
|
|
|
|
.B_INPUT("DIRECT"),
|
|
|
|
.BREG(0),
|
|
|
|
.CARRYINREG(0),
|
|
|
|
.CARRYINSELREG(0),
|
|
|
|
.CREG(0),
|
|
|
|
.DREG(0),
|
|
|
|
.INMODEREG(0),
|
|
|
|
.MREG(0),
|
|
|
|
.OPMODEREG(0),
|
|
|
|
.PREG(0)
|
|
|
|
) _TECHMAP_REPLACE_ (
|
|
|
|
//Data path
|
2019-07-16 17:54:27 -05:00
|
|
|
.A({{5{A[24]}}, A}),
|
2019-07-16 16:30:25 -05:00
|
|
|
.B(B),
|
2019-07-15 16:18:44 -05:00
|
|
|
.C(48'b0),
|
|
|
|
.D(24'b0),
|
|
|
|
.P(P_48),
|
|
|
|
|
|
|
|
.INMODE(4'b0000),
|
|
|
|
.ALUMODE(4'b0000),
|
|
|
|
.OPMODE(7'b000101),
|
|
|
|
.CARRYINSEL(3'b000),
|
|
|
|
|
|
|
|
.ACIN(30'b0),
|
|
|
|
.BCIN(18'b0),
|
|
|
|
.PCIN(48'b0),
|
|
|
|
.CARRYIN(1'b0)
|
|
|
|
);
|
|
|
|
assign Y = P_48;
|
|
|
|
endmodule
|