mirror of https://github.com/YosysHQ/yosys.git
41 lines
693 B
Verilog
41 lines
693 B
Verilog
module \$__MUL25X18 (input signed [24:0] A, input signed [17:0] B, output signed [42:0] Y);
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wire [47:0] P_48;
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DSP48E1 #(
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// Disable all registers
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.ACASCREG(0),
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.ADREG(0),
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.A_INPUT("DIRECT"),
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.ALUMODEREG(0),
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.AREG(0),
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.BCASCREG(0),
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.B_INPUT("DIRECT"),
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.BREG(0),
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.CARRYINREG(0),
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.CARRYINSELREG(0),
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.CREG(0),
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.DREG(0),
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.INMODEREG(0),
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.MREG(0),
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.OPMODEREG(0),
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.PREG(0)
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) _TECHMAP_REPLACE_ (
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//Data path
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.A({{5{A[24]}}, A}),
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.B(B),
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.C(48'b0),
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.D(24'b0),
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.P(P_48),
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.INMODE(4'b0000),
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.ALUMODE(4'b0000),
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.OPMODE(7'b000101),
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.CARRYINSEL(3'b000),
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.ACIN(30'b0),
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.BCIN(18'b0),
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.PCIN(48'b0),
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.CARRYIN(1'b0)
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);
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assign Y = P_48;
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endmodule
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