mirror of https://github.com/YosysHQ/yosys.git
7 lines
137 B
Plaintext
7 lines
137 B
Plaintext
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read_verilog sdffe.v
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proc
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opt_dff
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stat
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select -assert-count 1 t:$sdffe
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sim -clock clk -r tb_sdffe.fst -scope tb_sdffe.uut -sim-cmp sdffe
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