yosys/tests/arch/efinix/dffs.ys

read_verilog ../common/dffs.v
design -save read

hierarchy -top dff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE

select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D

design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE

select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
Share common tests 2019-10-18 05:19:59 -05:00			`read_verilog ../common/dffs.v`
split rest od ff's 2019-10-04 05:51:45 -05:00			`design -save read`

			`hierarchy -top dff`
hierarchy - proc reorder 2019-10-18 02:13:06 -05:00			`proc`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check`
			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
split rest od ff's 2019-10-04 05:51:45 -05:00			`cd dff # Constrain all select calls below inside the top module`
			`select -assert-count 1 t:EFX_FF`
			`select -assert-count 1 t:EFX_GBUFCE`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00
split rest od ff's 2019-10-04 05:51:45 -05:00			`select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D`

			`design -load read`
			`hierarchy -top dffe`
hierarchy - proc reorder 2019-10-18 02:13:06 -05:00			`proc`
split rest od ff's 2019-10-04 05:51:45 -05:00			`equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check`
			`design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)`
			`cd dffe # Constrain all select calls below inside the top module`
			`select -assert-count 1 t:EFX_FF`
Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. 2019-09-23 07:51:41 -05:00			`select -assert-count 1 t:EFX_GBUFCE`
split rest od ff's 2019-10-04 05:51:45 -05:00
Replace opt_rmdff with opt_dff. 2020-07-20 16:19:51 -05:00			`select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D`