yosys/tests/arch
Marcelina Kościelnicka 4e70c30775 FfData: some refactoring.
- FfData now keeps track of the module and underlying cell, if any (so
  calling emit on FfData created from a cell will replace the existing cell)
- FfData implementation is split off to its own .cc file for faster
  compilation
- the "flip FF data sense by inserting inverters in front and after"
  functionality that zinit uses is moved onto FfData class and beefed up
  to have dffsr support, to support more use cases
2021-10-07 04:24:06 +02:00
..
anlogic memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
common Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
ecp5 abc9: replace cell type/parameters if derived type already processed (#2991) 2021-09-09 10:05:55 -07:00
efinix tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
gowin Gowin: deal with active-low tristate (#2971) 2021-08-20 21:21:06 +02:00
ice40 test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. 2021-08-11 14:52:38 +02:00
intel_alm memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
machxo2 machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values. 2021-02-23 17:39:58 +01:00
nexus memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
quicklogic quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
xilinx FfData: some refactoring. 2021-10-07 04:24:06 +02:00
run-test.sh Add default assignments to SB_LUT4 2021-04-20 12:46:21 +02:00