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yosys/tests/arch/ecp5/lutram.ys

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Rename memory tests to lutram, add more xilinx tests
2019-12-12 19:44:37 -06:00
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
proc
memory -nomap
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
Uncomment sat command in memory.ys test.
2019-09-03 04:11:12 -05:00
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
design -load postopt
Rename memory tests to lutram, add more xilinx tests
2019-12-12 19:44:37 -06:00
cd lutram_1w1r
memory_bram: Reuse extract_rdff helper for make_outreg. Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
2021-05-25 12:31:53 -05:00
select -assert-count 8 t:L6MUX21
select -assert-count 36 t:LUT4
select -assert-count 16 t:PFUMX
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
select -assert-count 8 t:TRELLIS_DPR16X4
memory_bram: Reuse extract_rdff helper for make_outreg. Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
2021-05-25 12:31:53 -05:00
select -assert-count 8 t:TRELLIS_FF
Add tests for ECP5 architecture
2019-09-03 03:53:37 -05:00
select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D