2019-08-21 13:52:07 -05:00
|
|
|
read_verilog latches.v
|
2019-08-28 14:21:15 -05:00
|
|
|
|
|
|
|
|
proc
|
|
|
|
|
flatten
|
2019-10-03 12:45:53 -05:00
|
|
|
# Can't run any sort of equivalence check because latches are blown to LUTs
|
|
|
|
|
#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
2019-08-28 14:21:15 -05:00
|
|
|
|
2019-10-03 12:45:53 -05:00
|
|
|
#design -load preopt
|
2019-08-19 23:50:05 -05:00
|
|
|
synth_ice40
|
2019-08-22 14:30:49 -05:00
|
|
|
cd top
|
|
|
|
|
select -assert-count 4 t:SB_LUT4
|
|
|
|
|
select -assert-none t:SB_LUT4 %% t:* %D
|
